Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184468 |
1 |
|
|
T1 |
2 |
|
T2 |
358 |
|
T3 |
216 |
auto[1] |
234154 |
1 |
|
|
T1 |
54 |
|
T14 |
194 |
|
T15 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
104231 |
1 |
|
|
T1 |
14 |
|
T2 |
87 |
|
T3 |
48 |
lower_val |
103922 |
1 |
|
|
T1 |
6 |
|
T2 |
86 |
|
T3 |
65 |
zero_val |
1465 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
209396 |
1 |
|
|
T1 |
34 |
|
T2 |
162 |
|
T3 |
98 |
lower_val |
209216 |
1 |
|
|
T1 |
22 |
|
T2 |
196 |
|
T3 |
118 |
zero_val |
10 |
1 |
|
|
T146 |
2 |
|
T147 |
2 |
|
T148 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
22877 |
1 |
|
|
T2 |
38 |
|
T3 |
24 |
|
T4 |
1 |
higher_val |
higher_val |
auto[1] |
29193 |
1 |
|
|
T1 |
7 |
|
T14 |
19 |
|
T15 |
580 |
higher_val |
lower_val |
auto[0] |
22909 |
1 |
|
|
T2 |
49 |
|
T3 |
24 |
|
T13 |
7 |
higher_val |
lower_val |
auto[1] |
29249 |
1 |
|
|
T1 |
7 |
|
T14 |
31 |
|
T15 |
571 |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T146 |
2 |
|
T148 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
22641 |
1 |
|
|
T2 |
39 |
|
T3 |
34 |
|
T13 |
7 |
lower_val |
higher_val |
auto[1] |
29529 |
1 |
|
|
T1 |
4 |
|
T14 |
27 |
|
T15 |
539 |
lower_val |
lower_val |
auto[0] |
22543 |
1 |
|
|
T2 |
47 |
|
T3 |
31 |
|
T13 |
11 |
lower_val |
lower_val |
auto[1] |
29209 |
1 |
|
|
T1 |
2 |
|
T14 |
28 |
|
T15 |
519 |
zero_val |
higher_val |
auto[0] |
531 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
206 |
1 |
|
|
T1 |
1 |
|
T15 |
8 |
|
T16 |
1 |
zero_val |
lower_val |
auto[0] |
569 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
159 |
1 |
|
|
T1 |
1 |
|
T15 |
6 |
|
T16 |
3 |