Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 6121 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 6768 1 T3 27 T15 38 T16 20
len_5001_7500 11812 1 T3 46 T15 36 T16 49
len_2501_5000 7175 1 T3 12 T15 36 T16 15
len_1025_2500 4183 1 T3 7 T15 22 T16 5
len_769_1024 5793 1 T1 4 T2 32 T3 2
len_513_768 6218 1 T1 3 T2 37 T3 2
len_257_512 12504 1 T1 4 T2 34 T3 2
len_0_256 142001 1 T1 5 T2 40 T3 10
len_keccak_block_sizes[72] 529 1 T1 1 T15 3 T19 2
len_keccak_block_sizes[104] 433 1 T15 3 T19 2 T87 2
len_keccak_block_sizes[136] 334 1 T15 3 T87 2 T129 2
len_keccak_block_sizes[144] 238 1 T15 3 T129 2 T36 1
len_keccak_block_sizes[168] 151 1 T15 3 T174 3 T175 1
len_1 575 1 T15 3 T19 2 T87 2
len_0 1006 1 T15 3 T16 7 T19 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%