Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	67416218	1			T1	2394		T2	21167		T3	168478
all_pins[1]	67416218	1			T1	2394		T2	21167		T3	168478
all_pins[2]	67416218	1			T1	2394		T2	21167		T3	168478

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	201657111	1			T1	7164		T2	63291		T3	505272
values[0x1]	591543	1			T1	18		T2	210		T3	162
transitions[0x0=>0x1]	589716	1			T1	18		T2	210		T3	162
transitions[0x1=>0x0]	589737	1			T1	18		T2	210		T3	162

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	67113694	1			T1	2376		T2	20957		T3	168316
all_pins[0]	values[0x1]	302524	1			T1	18		T2	210		T3	162
all_pins[0]	transitions[0x0=>0x1]	302506	1			T1	18		T2	210		T3	162
all_pins[0]	transitions[0x1=>0x0]	54	1			T16	3		T95	2		T160	4
all_pins[1]	values[0x0]	67416146	1			T1	2394		T2	21167		T3	168478
all_pins[1]	values[0x1]	72	1			T16	3		T95	2		T160	4
all_pins[1]	transitions[0x0=>0x1]	57	1			T16	3		T95	2		T160	4
all_pins[1]	transitions[0x1=>0x0]	288932	1			T16	1515		T23	4167		T37	345
all_pins[2]	values[0x0]	67127271	1			T1	2394		T2	21167		T3	168478
all_pins[2]	values[0x1]	288947	1			T16	1515		T23	4167		T37	345
all_pins[2]	transitions[0x0=>0x1]	287153	1			T16	1505		T23	4139		T37	345
all_pins[2]	transitions[0x1=>0x0]	300751	1			T1	18		T2	210		T3	162