Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 8184505 | 1 |  |  | T1 | 3215 |  | T2 | 25635 |  | T3 | 17629 | 
| auto[1] | 17606392 | 1 |  |  | T1 | 4932 |  | T2 | 37980 |  | T3 | 25460 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 25724610 | 1 |  |  | T1 | 8134 |  | T2 | 63501 |  | T3 | 43011 | 
| triple_byte_access | 22015 | 1 |  |  | T1 | 3 |  | T2 | 39 |  | T3 | 16 | 
| halfword_access | 22173 | 1 |  |  | T1 | 6 |  | T2 | 32 |  | T3 | 33 | 
| byte_access | 22099 | 1 |  |  | T1 | 4 |  | T2 | 43 |  | T3 | 29 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | [triple_byte_access , halfword_access , byte_access] | -- | -- | 3 |  | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | word_access | 8118218 | 1 |  |  | T1 | 3202 |  | T2 | 25521 |  | T3 | 17551 | 
| auto[0] | triple_byte_access | 22015 | 1 |  |  | T1 | 3 |  | T2 | 39 |  | T3 | 16 | 
| auto[0] | halfword_access | 22173 | 1 |  |  | T1 | 6 |  | T2 | 32 |  | T3 | 33 | 
| auto[0] | byte_access | 22099 | 1 |  |  | T1 | 4 |  | T2 | 43 |  | T3 | 29 | 
| auto[1] | word_access | 17606392 | 1 |  |  | T1 | 4932 |  | T2 | 37980 |  | T3 | 25460 |