Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	68230035	1			T1	47176		T2	159230		T3	17370
all_values[1]	68230035	1			T1	47176		T2	159230		T3	17370
all_values[2]	68230035	1			T1	47176		T2	159230		T3	17370

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

498387

1

T1

7127

T2

6

T3

378

auto[1]

204191718

1

T1

134401

T2

477684

T3

51732

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203748282

1

T1

141390

T2

476334

T3

51621

auto[1]

941823

1

T1

138

T2

1356

T3

489

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	155777	1			T1	4207		T15	324		T16	558
all_values[0]	auto[0]	auto[1]	1743	1			T1	8		T15	10		T16	6
all_values[0]	auto[1]	auto[0]	67760317	1			T1	42923		T2	158778		T3	17207
all_values[0]	auto[1]	auto[1]	312198	1			T1	38		T2	452		T3	163
all_values[1]	auto[0]	auto[0]	174019	1			T2	2		T3	194		T14	2
all_values[1]	auto[0]	auto[1]	1398	1			T2	1		T3	3		T14	1
all_values[1]	auto[1]	auto[0]	67742075	1			T1	47130		T2	158776		T3	17013
all_values[1]	auto[1]	auto[1]	312543	1			T1	46		T2	451		T3	160
all_values[2]	auto[0]	auto[0]	164065	1			T1	2910		T2	2		T3	180
all_values[2]	auto[0]	auto[1]	1385	1			T1	2		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	67752029	1			T1	44220		T2	158776		T3	17027
all_values[2]	auto[1]	auto[1]	312556	1			T1	44		T2	451		T3	162