Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
226858 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
242 |
auto[1] |
206244 |
1 |
|
|
T1 |
60 |
|
T2 |
618 |
|
T13 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
108298 |
1 |
|
|
T1 |
14 |
|
T2 |
144 |
|
T3 |
62 |
lower_val |
107020 |
1 |
|
|
T1 |
14 |
|
T2 |
162 |
|
T3 |
70 |
zero_val |
1450 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
216994 |
1 |
|
|
T1 |
28 |
|
T2 |
320 |
|
T3 |
138 |
lower_val |
216100 |
1 |
|
|
T1 |
34 |
|
T2 |
300 |
|
T3 |
104 |
zero_val |
8 |
1 |
|
|
T176 |
2 |
|
T177 |
2 |
|
T178 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
[auto[1]] |
-- |
-- |
3 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
28295 |
1 |
|
|
T3 |
40 |
|
T14 |
1 |
|
T47 |
95 |
higher_val |
higher_val |
auto[1] |
25995 |
1 |
|
|
T1 |
7 |
|
T2 |
76 |
|
T13 |
96 |
higher_val |
lower_val |
auto[0] |
28203 |
1 |
|
|
T3 |
22 |
|
T47 |
92 |
|
T48 |
88 |
higher_val |
lower_val |
auto[1] |
25803 |
1 |
|
|
T1 |
7 |
|
T2 |
68 |
|
T13 |
116 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T176 |
1 |
|
T177 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
28171 |
1 |
|
|
T2 |
1 |
|
T3 |
42 |
|
T45 |
1 |
lower_val |
higher_val |
auto[1] |
25446 |
1 |
|
|
T1 |
5 |
|
T2 |
80 |
|
T13 |
69 |
lower_val |
lower_val |
auto[0] |
28207 |
1 |
|
|
T3 |
28 |
|
T46 |
4 |
|
T47 |
103 |
lower_val |
lower_val |
auto[1] |
25195 |
1 |
|
|
T1 |
9 |
|
T2 |
81 |
|
T13 |
71 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T176 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
565 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
152 |
1 |
|
|
T49 |
1 |
|
T31 |
2 |
|
T52 |
1 |
zero_val |
lower_val |
auto[0] |
584 |
1 |
|
|
T1 |
1 |
|
T18 |
1 |
|
T46 |
1 |
zero_val |
lower_val |
auto[1] |
148 |
1 |
|
|
T52 |
1 |
|
T179 |
2 |
|
T180 |
1 |
zero_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T181 |
1 |
|
- |
- |
|
- |
- |