Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	68230035	1			T1	47176		T2	159230		T3	17370
all_pins[1]	68230035	1			T1	47176		T2	159230		T3	17370
all_pins[2]	68230035	1			T1	47176		T2	159230		T3	17370

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	204082798	1			T1	141490		T2	477238		T3	50650
values[0x1]	607307	1			T1	38		T2	452		T3	1460
transitions[0x0=>0x1]	605485	1			T1	38		T2	452		T3	1460
transitions[0x1=>0x0]	605515	1			T1	38		T2	452		T3	1460

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	67917837	1			T1	47138		T2	158778		T3	17207
all_pins[0]	values[0x1]	312198	1			T1	38		T2	452		T3	163
all_pins[0]	transitions[0x0=>0x1]	312191	1			T1	38		T2	452		T3	163
all_pins[0]	transitions[0x1=>0x0]	85	1			T56	6		T196	2		T197	2
all_pins[1]	values[0x0]	68229943	1			T1	47176		T2	159230		T3	17370
all_pins[1]	values[0x1]	92	1			T56	6		T196	2		T197	2
all_pins[1]	transitions[0x0=>0x1]	72	1			T56	6		T196	2		T197	2
all_pins[1]	transitions[0x1=>0x0]	294997	1			T3	1297		T30	1184		T24	5790
all_pins[2]	values[0x0]	67935018	1			T1	47176		T2	159230		T3	16073
all_pins[2]	values[0x1]	295017	1			T3	1297		T30	1184		T24	5790
all_pins[2]	transitions[0x0=>0x1]	293222	1			T3	1297		T30	1184		T24	5751
all_pins[2]	transitions[0x1=>0x0]	310433	1			T1	38		T2	452		T3	163