Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	66652250	1			T2	16466		T3	251		T12	8460
all_values[1]	66652250	1			T2	16466		T3	251		T12	8460
all_values[2]	66652250	1			T2	16466		T3	251		T12	8460

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

446285

1

T2

131

T3

12

T12

446

auto[1]

199510465

1

T2

49267

T3

741

T12

24934

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

199054749

1

T2

48819

T3

714

T12

25080

auto[1]

902001

1

T2

579

T3

39

T12

300

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	175313	1			T3	4		T13	1		T14	1
all_values[0]	auto[0]	auto[1]	1979	1			T3	2		T14	2		T15	6
all_values[0]	auto[1]	auto[0]	66176270	1			T2	16273		T3	234		T12	8360
all_values[0]	auto[1]	auto[1]	298688	1			T2	193		T3	11		T12	100
all_values[1]	auto[0]	auto[0]	134410	1			T2	129		T12	222		T14	4
all_values[1]	auto[0]	auto[1]	1397	1			T2	2		T12	1		T14	3
all_values[1]	auto[1]	auto[0]	66217173	1			T2	16144		T3	238		T12	8138
all_values[1]	auto[1]	auto[1]	299270	1			T2	191		T3	13		T12	99
all_values[2]	auto[0]	auto[0]	131742	1			T3	4		T12	222		T13	399
all_values[2]	auto[0]	auto[1]	1444	1			T3	2		T12	1		T13	4
all_values[2]	auto[1]	auto[0]	66219841	1			T2	16273		T3	234		T12	8138
all_values[2]	auto[1]	auto[1]	299223	1			T2	193		T3	11		T12	99