Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
226082 |
1 |
|
|
T2 |
2 |
|
T3 |
18 |
|
T12 |
2 |
auto[1] |
189124 |
1 |
|
|
T2 |
380 |
|
T12 |
164 |
|
T13 |
394 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
103477 |
1 |
|
|
T2 |
110 |
|
T3 |
8 |
|
T12 |
34 |
lower_val |
102885 |
1 |
|
|
T2 |
84 |
|
T3 |
4 |
|
T12 |
43 |
zero_val |
1529 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
208610 |
1 |
|
|
T2 |
192 |
|
T3 |
10 |
|
T12 |
92 |
lower_val |
206584 |
1 |
|
|
T2 |
190 |
|
T3 |
8 |
|
T12 |
74 |
zero_val |
12 |
1 |
|
|
T153 |
2 |
|
T154 |
2 |
|
T155 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
28301 |
1 |
|
|
T3 |
5 |
|
T14 |
93 |
|
T17 |
37 |
higher_val |
higher_val |
auto[1] |
23712 |
1 |
|
|
T2 |
58 |
|
T12 |
20 |
|
T13 |
46 |
higher_val |
lower_val |
auto[0] |
28162 |
1 |
|
|
T3 |
3 |
|
T13 |
1 |
|
T14 |
97 |
higher_val |
lower_val |
auto[1] |
23300 |
1 |
|
|
T2 |
52 |
|
T12 |
14 |
|
T13 |
55 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T154 |
1 |
|
T156 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
28157 |
1 |
|
|
T12 |
1 |
|
T14 |
88 |
|
T17 |
47 |
lower_val |
higher_val |
auto[1] |
23503 |
1 |
|
|
T2 |
40 |
|
T12 |
28 |
|
T13 |
47 |
lower_val |
lower_val |
auto[0] |
27657 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T14 |
98 |
lower_val |
lower_val |
auto[1] |
23564 |
1 |
|
|
T2 |
43 |
|
T12 |
14 |
|
T13 |
39 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T153 |
2 |
|
T154 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
595 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
170 |
1 |
|
|
T82 |
2 |
|
T25 |
3 |
|
T23 |
1 |
zero_val |
lower_val |
auto[0] |
586 |
1 |
|
|
T2 |
1 |
|
T13 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
178 |
1 |
|
|
T25 |
5 |
|
T23 |
2 |
|
T100 |
2 |