Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	66652250	1			T2	16466		T3	251		T12	8460
all_pins[1]	66652250	1			T2	16466		T3	251		T12	8460
all_pins[2]	66652250	1			T2	16466		T3	251		T12	8460

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	199350790	1			T2	49205		T3	742		T12	25280
values[0x1]	605960	1			T2	193		T3	11		T12	100
transitions[0x0=>0x1]	604051	1			T2	193		T3	11		T12	100
transitions[0x1=>0x0]	604076	1			T2	193		T3	11		T12	100

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	66353562	1			T2	16273		T3	240		T12	8360
all_pins[0]	values[0x1]	298688	1			T2	193		T3	11		T12	100
all_pins[0]	transitions[0x0=>0x1]	298671	1			T2	193		T3	11		T12	100
all_pins[0]	transitions[0x1=>0x0]	66	1			T32	4		T165	6		T166	2
all_pins[1]	values[0x0]	66652167	1			T2	16466		T3	251		T12	8460
all_pins[1]	values[0x1]	83	1			T32	4		T165	6		T166	2
all_pins[1]	transitions[0x0=>0x1]	67	1			T32	4		T165	6		T166	2
all_pins[1]	transitions[0x1=>0x0]	307173	1			T15	726		T17	1073		T22	3732
all_pins[2]	values[0x0]	66345061	1			T2	16466		T3	251		T12	8460
all_pins[2]	values[0x1]	307189	1			T15	726		T17	1073		T22	3732
all_pins[2]	transitions[0x0=>0x1]	305313	1			T15	726		T17	1073		T22	3706
all_pins[2]	transitions[0x1=>0x0]	296837	1			T2	193		T3	11		T12	100