Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8348119 |
1 |
|
|
T2 |
22395 |
|
T3 |
96 |
|
T12 |
11427 |
auto[1] |
17759382 |
1 |
|
|
T2 |
34352 |
|
T3 |
450 |
|
T12 |
16830 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
26042143 |
1 |
|
|
T2 |
56664 |
|
T3 |
546 |
|
T12 |
28212 |
triple_byte_access |
21838 |
1 |
|
|
T2 |
30 |
|
T12 |
15 |
|
T13 |
30 |
halfword_access |
21691 |
1 |
|
|
T2 |
24 |
|
T12 |
16 |
|
T13 |
35 |
byte_access |
21829 |
1 |
|
|
T2 |
29 |
|
T12 |
14 |
|
T13 |
32 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
8282761 |
1 |
|
|
T2 |
22312 |
|
T3 |
96 |
|
T12 |
11382 |
auto[0] |
triple_byte_access |
21838 |
1 |
|
|
T2 |
30 |
|
T12 |
15 |
|
T13 |
30 |
auto[0] |
halfword_access |
21691 |
1 |
|
|
T2 |
24 |
|
T12 |
16 |
|
T13 |
35 |
auto[0] |
byte_access |
21829 |
1 |
|
|
T2 |
29 |
|
T12 |
14 |
|
T13 |
32 |
auto[1] |
word_access |
17759382 |
1 |
|
|
T2 |
34352 |
|
T3 |
450 |
|
T12 |
16830 |