Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	60851761	1			T2	215293		T3	87869		T4	186601
all_values[1]	60851761	1			T2	215293		T3	87869		T4	186601
all_values[2]	60851761	1			T2	215293		T3	87869		T4	186601

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

431437

1

T2

3

T3

580

T4

9795

auto[1]

182123846

1

T2

645876

T3

263027

T4

550008

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181748211

1

T2

644220

T3

261849

T4

558462

auto[1]

807072

1

T2

1659

T3

1758

T4

1341

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	153947	1			T3	235		T4	4467		T14	408
all_values[0]	auto[0]	auto[1]	1933	1			T3	6		T4	8		T14	4
all_values[0]	auto[1]	auto[0]	60428790	1			T2	214740		T3	87048		T4	181687
all_values[0]	auto[1]	auto[1]	267091	1			T2	553		T3	580		T4	439
all_values[1]	auto[0]	auto[0]	135472	1			T2	2		T3	326		T4	2945
all_values[1]	auto[0]	auto[1]	1429	1			T2	1		T3	7		T4	9
all_values[1]	auto[1]	auto[0]	60447265	1			T2	214738		T3	86957		T4	183209
all_values[1]	auto[1]	auto[1]	267595	1			T2	552		T3	579		T4	438
all_values[2]	auto[0]	auto[0]	137214	1			T3	5		T4	2350		T14	265
all_values[2]	auto[0]	auto[1]	1442	1			T3	1		T4	16		T14	2
all_values[2]	auto[1]	auto[0]	60445523	1			T2	214740		T3	87278		T4	183804
all_values[2]	auto[1]	auto[1]	267582	1			T2	553		T3	585		T4	431