Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183502 |
1 |
|
|
T2 |
2 |
|
T3 |
280 |
|
T4 |
398 |
auto[1] |
188840 |
1 |
|
|
T2 |
746 |
|
T3 |
588 |
|
T4 |
226 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
92664 |
1 |
|
|
T2 |
174 |
|
T3 |
240 |
|
T4 |
143 |
lower_val |
91930 |
1 |
|
|
T2 |
178 |
|
T3 |
218 |
|
T4 |
154 |
zero_val |
1438 |
1 |
|
|
T2 |
3 |
|
T3 |
8 |
|
T4 |
9 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
185646 |
1 |
|
|
T2 |
350 |
|
T3 |
432 |
|
T4 |
324 |
lower_val |
186696 |
1 |
|
|
T2 |
398 |
|
T3 |
436 |
|
T4 |
300 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
22442 |
1 |
|
|
T2 |
1 |
|
T3 |
29 |
|
T4 |
38 |
higher_val |
higher_val |
auto[1] |
23769 |
1 |
|
|
T2 |
72 |
|
T3 |
82 |
|
T4 |
27 |
higher_val |
lower_val |
auto[0] |
22790 |
1 |
|
|
T3 |
41 |
|
T4 |
51 |
|
T14 |
1 |
higher_val |
lower_val |
auto[1] |
23663 |
1 |
|
|
T2 |
101 |
|
T3 |
88 |
|
T4 |
27 |
lower_val |
higher_val |
auto[0] |
22350 |
1 |
|
|
T3 |
41 |
|
T4 |
47 |
|
T16 |
16 |
lower_val |
higher_val |
auto[1] |
23356 |
1 |
|
|
T2 |
81 |
|
T3 |
72 |
|
T4 |
33 |
lower_val |
lower_val |
auto[0] |
22746 |
1 |
|
|
T3 |
46 |
|
T4 |
51 |
|
T16 |
14 |
lower_val |
lower_val |
auto[1] |
23478 |
1 |
|
|
T2 |
97 |
|
T3 |
59 |
|
T4 |
23 |
zero_val |
higher_val |
auto[0] |
563 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
2 |
zero_val |
higher_val |
auto[1] |
173 |
1 |
|
|
T3 |
2 |
|
T4 |
4 |
|
T16 |
2 |
zero_val |
lower_val |
auto[0] |
550 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
152 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T16 |
1 |