Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	60851761	1			T2	215293		T3	87869		T4	186601
all_pins[1]	60851761	1			T2	215293		T3	87869		T4	186601
all_pins[2]	60851761	1			T2	215293		T3	87869		T4	186601

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	181974490	1			T2	645326		T3	257881		T4	559017
values[0x1]	580793	1			T2	553		T3	5726		T4	786
transitions[0x0=>0x1]	578882	1			T2	553		T3	5688		T4	784
transitions[0x1=>0x0]	578912	1			T2	553		T3	5688		T4	784

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	60584670	1			T2	214740		T3	87289		T4	186162
all_pins[0]	values[0x1]	267091	1			T2	553		T3	580		T4	439
all_pins[0]	transitions[0x0=>0x1]	267081	1			T2	553		T3	580		T4	439
all_pins[0]	transitions[0x1=>0x0]	79	1			T41	2		T166	2		T39	7
all_pins[1]	values[0x0]	60851672	1			T2	215293		T3	87869		T4	186601
all_pins[1]	values[0x1]	89	1			T41	2		T166	2		T39	7
all_pins[1]	transitions[0x0=>0x1]	82	1			T41	2		T166	2		T39	7
all_pins[1]	transitions[0x1=>0x0]	313606	1			T3	5146		T4	347		T14	16430
all_pins[2]	values[0x0]	60538148	1			T2	215293		T3	82723		T4	186254
all_pins[2]	values[0x1]	313613	1			T3	5146		T4	347		T14	16430
all_pins[2]	transitions[0x0=>0x1]	311719	1			T3	5108		T4	345		T14	16316
all_pins[2]	transitions[0x1=>0x0]	265227	1			T2	553		T3	542		T4	437