Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	617	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5288	1			T3	42		T4	31		T14	15
len_601_800	11826	1			T3	80		T4	76		T14	44
len_401_600	7985	1			T3	61		T4	47		T14	32
len_201_400	8536	1			T3	29		T4	25		T14	16
len_65_200	26650	1			T3	82		T4	50		T13	91
len_min_for_xof_require_squeeze	342	1			T3	3		T185	1		T25	1
len_keccak_block_sizes[72]	258	1			T3	1		T186	1		T185	1
len_keccak_block_sizes[104]	253	1			T185	3		T183	9		T184	9
len_keccak_block_sizes[136]	255	1			T185	2		T183	9		T184	9
len_keccak_block_sizes[144]	129	1			T185	1		T187	1		T188	1
len_keccak_block_sizes[168]	120	1			T3	1		T189	2		T190	1
len_datapath_width	13567	1			T3	13		T4	14		T13	5
len_2_63	110402	1			T2	374		T3	120		T4	64
len_1	35	1			T4	2		T185	2		T25	1