Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 7955779 | 1 |  |  | T2 | 2992 |  | T3 | 46398 |  | T4 | 36298 | 
| auto[1] | 16502604 | 1 |  |  | T2 | 18700 |  | T3 | 71260 |  | T4 | 55044 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 24401268 | 1 |  |  | T2 | 21692 |  | T3 | 117385 |  | T4 | 91137 | 
| triple_byte_access | 18910 | 1 |  |  | T3 | 79 |  | T4 | 70 |  | T13 | 37 | 
| halfword_access | 19268 | 1 |  |  | T3 | 94 |  | T4 | 67 |  | T13 | 34 | 
| byte_access | 18937 | 1 |  |  | T3 | 100 |  | T4 | 68 |  | T13 | 42 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | [triple_byte_access , halfword_access , byte_access] | -- | -- | 3 |  | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | word_access | 7898664 | 1 |  |  | T2 | 2992 |  | T3 | 46125 |  | T4 | 36093 | 
| auto[0] | triple_byte_access | 18910 | 1 |  |  | T3 | 79 |  | T4 | 70 |  | T13 | 37 | 
| auto[0] | halfword_access | 19268 | 1 |  |  | T3 | 94 |  | T4 | 67 |  | T13 | 34 | 
| auto[0] | byte_access | 18937 | 1 |  |  | T3 | 100 |  | T4 | 68 |  | T13 | 42 | 
| auto[1] | word_access | 16502604 | 1 |  |  | T2 | 18700 |  | T3 | 71260 |  | T4 | 55044 |