Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	65495805	1			T1	5196		T2	293		T3	279
all_values[1]	65495805	1			T1	5196		T2	293		T3	279
all_values[2]	65495805	1			T1	5196		T2	293		T3	279

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

553278

1

T1

1659

T2

29

T3

14

auto[1]

195934137

1

T1

13929

T2

850

T3

823

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195627237

1

T1

15432

T2

843

T3

795

auto[1]

860178

1

T1

156

T2

36

T3

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	150375	1			T1	1637		T2	5		T17	1
all_values[0]	auto[0]	auto[1]	1901	1			T1	22		T2	2		T17	2
all_values[0]	auto[1]	auto[0]	65058704	1			T1	3507		T2	276		T3	265
all_values[0]	auto[1]	auto[1]	284825	1			T1	30		T2	10		T3	14
all_values[1]	auto[0]	auto[0]	183019	1			T2	12		T3	11		T16	13
all_values[1]	auto[0]	auto[1]	1499	1			T2	3		T3	3		T16	2
all_values[1]	auto[1]	auto[0]	65026060	1			T1	5144		T2	269		T3	254
all_values[1]	auto[1]	auto[1]	285227	1			T1	52		T2	9		T3	11
all_values[2]	auto[0]	auto[0]	214922	1			T2	5		T13	176		T14	3
all_values[2]	auto[0]	auto[1]	1562	1			T2	2		T13	2		T15	1
all_values[2]	auto[1]	auto[0]	64994157	1			T1	5144		T2	276		T3	265
all_values[2]	auto[1]	auto[1]	285164	1			T1	52		T2	10		T3	14