Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	65495805	1			T1	5196		T2	293		T3	279
all_pins[1]	65495805	1			T1	5196		T2	293		T3	279
all_pins[2]	65495805	1			T1	5196		T2	293		T3	279

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	195862086	1			T1	15243		T2	869		T3	823
values[0x1]	625329	1			T1	345		T2	10		T3	14
transitions[0x0=>0x1]	623192	1			T1	345		T2	10		T3	14
transitions[0x1=>0x0]	623213	1			T1	345		T2	10		T3	14

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	65210980	1			T1	5166		T2	283		T3	265
all_pins[0]	values[0x1]	284825	1			T1	30		T2	10		T3	14
all_pins[0]	transitions[0x0=>0x1]	284814	1			T1	30		T2	10		T3	14
all_pins[0]	transitions[0x1=>0x0]	54	1			T39	2		T131	2		T42	2
all_pins[1]	values[0x0]	65495740	1			T1	5196		T2	293		T3	279
all_pins[1]	values[0x1]	65	1			T39	2		T131	2		T42	2
all_pins[1]	transitions[0x0=>0x1]	51	1			T39	2		T131	2		T42	2
all_pins[1]	transitions[0x1=>0x0]	340425	1			T1	315		T15	293		T22	632
all_pins[2]	values[0x0]	65155366	1			T1	4881		T2	293		T3	279
all_pins[2]	values[0x1]	340439	1			T1	315		T15	293		T22	632
all_pins[2]	transitions[0x0=>0x1]	338327	1			T1	315		T15	293		T22	628
all_pins[2]	transitions[0x1=>0x0]	282734	1			T1	30		T2	10		T3	14