Summary for Variable in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for in_app_keymgr
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 196314 | 1 |  |  | T1 | 35 |  | T2 | 9 |  | T3 | 9 | 
| auto[1] | 3224 | 1 |  |  | T1 | 1 |  | T13 | 6 |  | T14 | 35 | 
Summary for Variable kmac_mode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for kmac_mode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 163393 | 1 |  |  | T1 | 5 |  | T13 | 39 |  | T14 | 92 | 
| auto[1] | 36145 | 1 |  |  | T1 | 31 |  | T2 | 9 |  | T3 | 9 | 
Summary for Variable sideload
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for sideload
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 186539 | 1 |  |  | T1 | 30 |  | T2 | 9 |  | T3 | 9 | 
| auto[1] | 12999 | 1 |  |  | T1 | 6 |  | T13 | 27 |  | T14 | 42 | 
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| User Defined Cross Bins | 4 | 0 | 4 | 100.00 |  | 
User Defined Cross Bins for sideload_cross
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| sw_kmac_valid_sideload | 12999 | 1 |  |  | T1 | 6 |  | T13 | 27 |  | T14 | 42 | 
| sw_kmac_invalid_sideload | 186539 | 1 |  |  | T1 | 30 |  | T2 | 9 |  | T3 | 9 | 
| app_valid_sideload | 12999 | 1 |  |  | T1 | 6 |  | T13 | 27 |  | T14 | 42 | 
| app_invalid_sideload | 186539 | 1 |  |  | T1 | 30 |  | T2 | 9 |  | T3 | 9 |