Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83007097	1			T1	10490		T2	320		T3	221601
all_values[1]	83007097	1			T1	10490		T2	320		T3	221601
all_values[2]	83007097	1			T1	10490		T2	320		T3	221601

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

556321

1

T1

636

T2

26

T3

10

auto[1]

248464970

1

T1

30834

T2

934

T3

664793

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

247815129

1

T1

31188

T2

924

T3

663078

auto[1]

1206162

1

T1

282

T2

36

T3

1725

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	197251	1			T1	126		T2	9		T13	14
all_values[0]	auto[0]	auto[1]	2002	1			T1	2		T2	4		T13	2
all_values[0]	auto[1]	auto[0]	82407792	1			T1	10270		T2	299		T3	221026
all_values[0]	auto[1]	auto[1]	400052	1			T1	92		T2	8		T3	575
all_values[1]	auto[0]	auto[0]	183680	1			T1	503		T3	2		T14	2
all_values[1]	auto[0]	auto[1]	1483	1			T1	5		T3	1		T14	1
all_values[1]	auto[1]	auto[0]	82421363	1			T1	9893		T2	308		T3	221024
all_values[1]	auto[1]	auto[1]	400571	1			T1	89		T2	12		T3	574
all_values[2]	auto[0]	auto[0]	170369	1			T2	9		T3	5		T12	212
all_values[2]	auto[0]	auto[1]	1536	1			T2	4		T3	2		T12	1
all_values[2]	auto[1]	auto[0]	82434674	1			T1	10396		T2	299		T3	221021
all_values[2]	auto[1]	auto[1]	400518	1			T1	94		T2	8		T3	573