Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
265488 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
780 |
auto[1] |
284434 |
1 |
|
|
T1 |
122 |
|
T12 |
210 |
|
T14 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
137315 |
1 |
|
|
T1 |
26 |
|
T2 |
8 |
|
T3 |
193 |
lower_val |
135951 |
1 |
|
|
T1 |
24 |
|
T2 |
4 |
|
T3 |
186 |
zero_val |
1601 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
274748 |
1 |
|
|
T1 |
70 |
|
T2 |
4 |
|
T3 |
366 |
lower_val |
275172 |
1 |
|
|
T1 |
54 |
|
T2 |
14 |
|
T3 |
414 |
zero_val |
2 |
1 |
|
|
T159 |
2 |
|
- |
- |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
33193 |
1 |
|
|
T2 |
1 |
|
T3 |
84 |
|
T13 |
15 |
higher_val |
higher_val |
auto[1] |
35758 |
1 |
|
|
T1 |
19 |
|
T12 |
27 |
|
T14 |
65 |
higher_val |
lower_val |
auto[0] |
33183 |
1 |
|
|
T2 |
7 |
|
T3 |
109 |
|
T13 |
15 |
higher_val |
lower_val |
auto[1] |
35180 |
1 |
|
|
T1 |
7 |
|
T12 |
33 |
|
T14 |
69 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T159 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
32748 |
1 |
|
|
T2 |
1 |
|
T3 |
87 |
|
T13 |
24 |
lower_val |
higher_val |
auto[1] |
35144 |
1 |
|
|
T1 |
14 |
|
T12 |
29 |
|
T14 |
86 |
lower_val |
lower_val |
auto[0] |
32360 |
1 |
|
|
T2 |
3 |
|
T3 |
99 |
|
T13 |
25 |
lower_val |
lower_val |
auto[1] |
35699 |
1 |
|
|
T1 |
10 |
|
T12 |
33 |
|
T14 |
84 |
zero_val |
higher_val |
auto[0] |
583 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
208 |
1 |
|
|
T14 |
2 |
|
T41 |
3 |
|
T23 |
1 |
zero_val |
lower_val |
auto[0] |
607 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
203 |
1 |
|
|
T41 |
3 |
|
T23 |
2 |
|
T24 |
1 |