Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	7775	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8181	1			T3	17		T13	21		T14	24
len_5001_7500	13772	1			T3	17		T13	39		T14	24
len_2501_5000	8412	1			T3	17		T13	11		T14	24
len_1025_2500	4924	1			T3	10		T13	5		T14	14
len_769_1024	5990	1			T1	18		T3	2		T12	22
len_513_768	6462	1			T1	18		T3	2		T12	32
len_257_512	13659	1			T1	13		T3	2		T12	30
len_0_256	198951	1			T1	13		T2	9		T3	290
len_keccak_block_sizes[72]	625	1			T3	2		T14	2		T15	2
len_keccak_block_sizes[104]	528	1			T3	2		T12	1		T14	2
len_keccak_block_sizes[136]	432	1			T1	1		T3	2		T15	2
len_keccak_block_sizes[144]	325	1			T3	2		T41	3		T108	3
len_keccak_block_sizes[168]	242	1			T17	1		T41	3		T23	1
len_1	651	1			T3	2		T14	2		T15	2
len_0	1109	1			T3	2		T13	2		T14	2