Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83007097	1			T1	10490		T2	320		T3	221601
all_pins[1]	83007097	1			T1	10490		T2	320		T3	221601
all_pins[2]	83007097	1			T1	10490		T2	320		T3	221601

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	248271746	1			T1	31378		T2	952		T3	664228
values[0x1]	749545	1			T1	92		T2	8		T3	575
transitions[0x0=>0x1]	747398	1			T1	92		T2	8		T3	575
transitions[0x1=>0x0]	747422	1			T1	92		T2	8		T3	575

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	82607045	1			T1	10398		T2	312		T3	221026
all_pins[0]	values[0x1]	400052	1			T1	92		T2	8		T3	575
all_pins[0]	transitions[0x0=>0x1]	400038	1			T1	92		T2	8		T3	575
all_pins[0]	transitions[0x1=>0x0]	84	1			T170	3		T51	3		T171	4
all_pins[1]	values[0x0]	83006999	1			T1	10490		T2	320		T3	221601
all_pins[1]	values[0x1]	98	1			T170	3		T51	3		T171	4
all_pins[1]	transitions[0x0=>0x1]	84	1			T170	3		T51	3		T171	4
all_pins[1]	transitions[0x1=>0x0]	349381	1			T17	732		T22	23359		T23	10158
all_pins[2]	values[0x0]	82657702	1			T1	10490		T2	320		T3	221601
all_pins[2]	values[0x1]	349395	1			T17	732		T22	23359		T23	10158
all_pins[2]	transitions[0x0=>0x1]	347276	1			T17	732		T22	23208		T23	10085
all_pins[2]	transitions[0x1=>0x0]	397957	1			T1	92		T2	8		T3	575