Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	684	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5558	1			T1	9		T12	15		T13	11
len_601_800	12368	1			T1	22		T12	45		T13	33
len_401_600	8461	1			T1	15		T12	26		T13	21
len_201_400	16240	1			T1	10		T12	9		T13	7
len_65_200	52671	1			T1	4		T12	5		T13	12
len_min_for_xof_require_squeeze	736	1			T41	10		T23	2		T108	10
len_keccak_block_sizes[72]	480	1			T41	5		T23	1		T108	5
len_keccak_block_sizes[104]	471	1			T41	5		T24	2		T108	5
len_keccak_block_sizes[136]	477	1			T13	1		T41	5		T108	5
len_keccak_block_sizes[144]	282	1			T41	5		T23	1		T108	5
len_keccak_block_sizes[168]	274	1			T41	5		T24	1		T108	5
len_datapath_width	13810	1			T2	3		T16	3		T17	1
len_2_63	164062	1			T1	2		T2	6		T3	390
len_1	54	1			T23	2		T24	2		T180	1