Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
270943 |
1 |
|
|
T1 |
62 |
|
T2 |
9 |
|
T3 |
383 |
auto[1] |
3334 |
1 |
|
|
T22 |
29 |
|
T23 |
24 |
|
T24 |
7 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
236697 |
1 |
|
|
T1 |
14 |
|
T3 |
383 |
|
T12 |
29 |
auto[1] |
37580 |
1 |
|
|
T1 |
48 |
|
T2 |
9 |
|
T12 |
75 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
260973 |
1 |
|
|
T2 |
9 |
|
T3 |
383 |
|
T13 |
86 |
auto[1] |
13304 |
1 |
|
|
T1 |
62 |
|
T12 |
104 |
|
T17 |
8 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13304 |
1 |
|
|
T1 |
62 |
|
T12 |
104 |
|
T17 |
8 |
sw_kmac_invalid_sideload |
260973 |
1 |
|
|
T2 |
9 |
|
T3 |
383 |
|
T13 |
86 |
app_valid_sideload |
13304 |
1 |
|
|
T1 |
62 |
|
T12 |
104 |
|
T17 |
8 |
app_invalid_sideload |
260973 |
1 |
|
|
T2 |
9 |
|
T3 |
383 |
|
T13 |
86 |