Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	90021437	1			T1	564339		T2	9066		T3	1816
all_values[1]	90021437	1			T1	564339		T2	9066		T3	1816
all_values[2]	90021437	1			T1	564339		T2	9066		T3	1816

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

513291

1

T1

28

T2

153

T3

166

auto[1]

269551020

1

T1

169298

T2

27045

T3

5282

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

268691919

1

T1

168248

T2

26967

T3

4965

auto[1]

1372392

1

T1

10533

T2

231

T3

483

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	170348	1			T1	11		T3	12		T13	491
all_values[0]	auto[0]	auto[1]	2097	1			T1	10		T3	2		T13	10
all_values[0]	auto[1]	auto[0]	89393625	1			T1	560817		T2	8989		T3	1643
all_values[0]	auto[1]	auto[1]	455367	1			T1	3501		T2	77		T3	159
all_values[1]	auto[0]	auto[0]	173037	1			T3	41		T17	18		T19	1
all_values[1]	auto[0]	auto[1]	1433	1			T3	4		T17	4		T19	2
all_values[1]	auto[1]	auto[0]	89390936	1			T1	560828		T2	8989		T3	1614
all_values[1]	auto[1]	auto[1]	456031	1			T1	3511		T2	77		T3	157
all_values[2]	auto[0]	auto[0]	164750	1			T1	3		T2	152		T3	100
all_values[2]	auto[0]	auto[1]	1626	1			T1	4		T2	1		T3	7
all_values[2]	auto[1]	auto[0]	89399223	1			T1	560825		T2	8837		T3	1555
all_values[2]	auto[1]	auto[1]	455838	1			T1	3507		T2	76		T3	154