Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	90021437	1			T1	564339		T2	9066		T3	1816
all_pins[1]	90021437	1			T1	564339		T2	9066		T3	1816
all_pins[2]	90021437	1			T1	564339		T2	9066		T3	1816

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	269313561	1			T1	168951		T2	26556		T3	5289
values[0x1]	750750	1			T1	3501		T2	642		T3	159
transitions[0x0=>0x1]	748918	1			T1	3501		T2	642		T3	159
transitions[0x1=>0x0]	748940	1			T1	3501		T2	642		T3	159

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89566070	1			T1	560838		T2	8989		T3	1657
all_pins[0]	values[0x1]	455367	1			T1	3501		T2	77		T3	159
all_pins[0]	transitions[0x0=>0x1]	455357	1			T1	3501		T2	77		T3	159
all_pins[0]	transitions[0x1=>0x0]	73	1			T43	5		T44	2		T180	4
all_pins[1]	values[0x0]	90021354	1			T1	564339		T2	9066		T3	1816
all_pins[1]	values[0x1]	83	1			T43	5		T44	2		T180	4
all_pins[1]	transitions[0x0=>0x1]	74	1			T43	5		T44	2		T180	4
all_pins[1]	transitions[0x1=>0x0]	295291	1			T2	565		T13	1006		T23	150
all_pins[2]	values[0x0]	89726137	1			T1	564339		T2	8501		T3	1816
all_pins[2]	values[0x1]	295300	1			T2	565		T13	1006		T23	150
all_pins[2]	transitions[0x0=>0x1]	293487	1			T2	565		T13	1006		T23	149
all_pins[2]	transitions[0x1=>0x0]	453576	1			T1	3501		T2	77		T3	159