Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 10030494 | 1 |  |  | T1 | 27235 |  | T2 | 8552 |  | T3 | 18466 | 
| auto[1] | 23612700 | 1 |  |  | T1 | 116850 |  | T2 | 12546 |  | T3 | 27152 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 33537216 | 1 |  |  | T1 | 143248 |  | T2 | 21057 |  | T3 | 45537 | 
| triple_byte_access | 35324 | 1 |  |  | T1 | 279 |  | T2 | 17 |  | T3 | 35 | 
| halfword_access | 35462 | 1 |  |  | T1 | 279 |  | T2 | 11 |  | T3 | 31 | 
| byte_access | 35192 | 1 |  |  | T1 | 279 |  | T2 | 13 |  | T3 | 15 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | [triple_byte_access , halfword_access , byte_access] | -- | -- | 3 |  | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | word_access | 9924516 | 1 |  |  | T1 | 26398 |  | T2 | 8511 |  | T3 | 18385 | 
| auto[0] | triple_byte_access | 35324 | 1 |  |  | T1 | 279 |  | T2 | 17 |  | T3 | 35 | 
| auto[0] | halfword_access | 35462 | 1 |  |  | T1 | 279 |  | T2 | 11 |  | T3 | 31 | 
| auto[0] | byte_access | 35192 | 1 |  |  | T1 | 279 |  | T2 | 13 |  | T3 | 15 | 
| auto[1] | word_access | 23612700 | 1 |  |  | T1 | 116850 |  | T2 | 12546 |  | T3 | 27152 |