Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15932844	1			T1	14323		T2	111445		T3	16685
all_values[1]	15932844	1			T1	14323		T2	111445		T3	16685
all_values[2]	15932844	1			T1	14323		T2	111445		T3	16685

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559568

1

T1

1

T2

255

T13

524

auto[1]

47238964

1

T1

42968

T2

334080

T3

50055

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47586369

1

T1

42573

T2

333885

T3

49617

auto[1]

212163

1

T1

396

T2

450

T3

438

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	183429	1			T16	8		T17	39		T19	4046
all_values[0]	auto[0]	auto[1]	1212	1			T16	2		T17	10		T19	4
all_values[0]	auto[1]	auto[0]	15678694	1			T1	14191		T2	111295		T3	16539
all_values[0]	auto[1]	auto[1]	69509	1			T1	132		T2	150		T3	146
all_values[1]	auto[0]	auto[0]	188262	1			T2	210		T13	522		T18	314
all_values[1]	auto[0]	auto[1]	986	1			T2	5		T13	2		T18	1
all_values[1]	auto[1]	auto[0]	15673861	1			T1	14191		T2	111085		T3	16539
all_values[1]	auto[1]	auto[1]	69735	1			T1	132		T2	145		T3	146
all_values[2]	auto[0]	auto[0]	184704	1			T1	1		T2	39		T14	5
all_values[2]	auto[0]	auto[1]	975	1			T2	1		T14	1		T19	6
all_values[2]	auto[1]	auto[0]	15677419	1			T1	14190		T2	111256		T3	16539
all_values[2]	auto[1]	auto[1]	69746	1			T1	132		T2	149		T3	146