Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50486 |
1 |
|
|
T1 |
256 |
|
T2 |
2 |
|
T3 |
230 |
auto[1] |
58436 |
1 |
|
|
T2 |
198 |
|
T14 |
4 |
|
T16 |
132 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27354 |
1 |
|
|
T1 |
62 |
|
T2 |
54 |
|
T3 |
60 |
lower_val |
26833 |
1 |
|
|
T1 |
78 |
|
T2 |
48 |
|
T3 |
68 |
zero_val |
877 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
54768 |
1 |
|
|
T1 |
128 |
|
T2 |
100 |
|
T3 |
126 |
lower_val |
54154 |
1 |
|
|
T1 |
128 |
|
T2 |
100 |
|
T3 |
104 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6228 |
1 |
|
|
T1 |
32 |
|
T3 |
38 |
|
T13 |
20 |
higher_val |
higher_val |
auto[1] |
7505 |
1 |
|
|
T2 |
33 |
|
T16 |
17 |
|
T18 |
25 |
higher_val |
lower_val |
auto[0] |
6187 |
1 |
|
|
T1 |
30 |
|
T3 |
22 |
|
T13 |
14 |
higher_val |
lower_val |
auto[1] |
7434 |
1 |
|
|
T2 |
21 |
|
T16 |
19 |
|
T18 |
19 |
lower_val |
higher_val |
auto[0] |
6366 |
1 |
|
|
T1 |
40 |
|
T3 |
29 |
|
T13 |
24 |
lower_val |
higher_val |
auto[1] |
7060 |
1 |
|
|
T2 |
18 |
|
T16 |
17 |
|
T18 |
31 |
lower_val |
lower_val |
auto[0] |
6271 |
1 |
|
|
T1 |
38 |
|
T3 |
39 |
|
T13 |
23 |
lower_val |
lower_val |
auto[1] |
7136 |
1 |
|
|
T2 |
30 |
|
T16 |
21 |
|
T18 |
27 |
zero_val |
higher_val |
auto[0] |
357 |
1 |
|
|
T13 |
1 |
|
T14 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
91 |
1 |
|
|
T18 |
1 |
|
T84 |
4 |
|
T37 |
1 |
zero_val |
lower_val |
auto[0] |
354 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
75 |
1 |
|
|
T18 |
1 |
|
T22 |
2 |
|
T37 |
6 |