Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	10765760	1			T1	8635		T3	13154		T13	6032
shake	5192287	1			T1	9955		T3	3673		T13	4075
sha3	1911478	1			T1	122		T2	111244		T3	697

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7102646

1

T1

10082

T2

111244

T3

4369

auto[1]

10766879

1

T1

8630

T3

13155

T13

6036

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	17012158	1			T1	17983		T2	111244		T3	17524
depth[0x01]	327411	1			T1	425		T13	266		T14	2
depth[0x02]	170637	1			T1	112		T13	72		T17	6069
depth[0x03]	140709	1			T1	119		T13	64		T17	5113
depth[0x04]	89145	1			T1	60		T13	26		T17	3366
depth[0x05]	53498	1			T1	13		T13	7		T17	2151
depth[0x06]	21745	1			T17	1074		T22	67		T38	515
depth[0x07]	403	1			T22	3		T76	69		T168	26
depth[0x08]	1779	1			T17	98		T22	7		T38	44
depth[0x09]	1478	1			T17	50		T22	7		T38	16
depth[0x0a]	50562	1			T17	2298		T22	231		T38	1036

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

857367

1

T1

729

T13

435

T14

2

auto[1]

17012158

1

T1

17983

T2

111244

T3

17524

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17818963

1

T1

18712

T2

111244

T3

17524

auto[1]

50562

1

T17

2298

T22

231

T38

1036