Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15932844	1			T1	14323		T2	111445		T3	16685
all_pins[1]	15932844	1			T1	14323		T2	111445		T3	16685
all_pins[2]	15932844	1			T1	14323		T2	111445		T3	16685

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47388781	1			T1	42837		T2	334185		T3	49182
values[0x1]	409751	1			T1	132		T2	150		T3	873
transitions[0x0=>0x1]	407635	1			T1	132		T2	150		T3	872
transitions[0x1=>0x0]	407659	1			T1	132		T2	150		T3	873

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15863335	1			T1	14191		T2	111295		T3	16539
all_pins[0]	values[0x1]	69509	1			T1	132		T2	150		T3	146
all_pins[0]	transitions[0x0=>0x1]	69495	1			T1	132		T2	150		T3	146
all_pins[0]	transitions[0x1=>0x0]	64	1			T17	3		T76	6		T151	3
all_pins[1]	values[0x0]	15932766	1			T1	14323		T2	111445		T3	16685
all_pins[1]	values[0x1]	78	1			T17	3		T76	6		T151	3
all_pins[1]	transitions[0x0=>0x1]	64	1			T17	3		T76	6		T151	3
all_pins[1]	transitions[0x1=>0x0]	340150	1			T3	727		T22	14279		T23	15875
all_pins[2]	values[0x0]	15592680	1			T1	14323		T2	111445		T3	15958
all_pins[2]	values[0x1]	340164	1			T3	727		T22	14279		T23	15875
all_pins[2]	transitions[0x0=>0x1]	338076	1			T3	726		T22	14181		T23	15776
all_pins[2]	transitions[0x1=>0x0]	67445	1			T1	132		T2	150		T3	146