Summary for Variable in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for in_app_keymgr
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 57519 | 1 |  |  | T1 | 151 |  | T2 | 94 |  | T3 | 118 | 
| auto[1] | 3610 | 1 |  |  | T1 | 11 |  | T3 | 3 |  | T13 | 13 | 
Summary for Variable kmac_mode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for kmac_mode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 26505 | 1 |  |  | T1 | 93 |  | T2 | 94 |  | T3 | 32 | 
| auto[1] | 34624 | 1 |  |  | T1 | 69 |  | T3 | 89 |  | T13 | 53 | 
Summary for Variable sideload
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for sideload
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 47096 | 1 |  |  | T1 | 122 |  | T2 | 94 |  | T3 | 97 | 
| auto[1] | 14033 | 1 |  |  | T1 | 40 |  | T3 | 24 |  | T13 | 24 | 
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| User Defined Cross Bins | 4 | 0 | 4 | 100.00 |  | 
User Defined Cross Bins for sideload_cross
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| sw_kmac_valid_sideload | 14033 | 1 |  |  | T1 | 40 |  | T3 | 24 |  | T13 | 24 | 
| sw_kmac_invalid_sideload | 47096 | 1 |  |  | T1 | 122 |  | T2 | 94 |  | T3 | 97 | 
| app_valid_sideload | 14033 | 1 |  |  | T1 | 40 |  | T3 | 24 |  | T13 | 24 | 
| app_invalid_sideload | 47096 | 1 |  |  | T1 | 122 |  | T2 | 94 |  | T3 | 97 |