Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6231385 |
1 |
|
|
T1 |
16892 |
|
T2 |
1600 |
|
T3 |
15769 |
auto[1] |
9513296 |
1 |
|
|
T1 |
25032 |
|
T2 |
5000 |
|
T3 |
23782 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15712991 |
1 |
|
|
T1 |
41848 |
|
T2 |
6600 |
|
T3 |
39476 |
triple_byte_access |
10596 |
1 |
|
|
T1 |
29 |
|
T3 |
32 |
|
T13 |
13 |
halfword_access |
10477 |
1 |
|
|
T1 |
28 |
|
T3 |
21 |
|
T13 |
19 |
byte_access |
10617 |
1 |
|
|
T1 |
19 |
|
T3 |
22 |
|
T13 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6199695 |
1 |
|
|
T1 |
16816 |
|
T2 |
1600 |
|
T3 |
15694 |
auto[0] |
triple_byte_access |
10596 |
1 |
|
|
T1 |
29 |
|
T3 |
32 |
|
T13 |
13 |
auto[0] |
halfword_access |
10477 |
1 |
|
|
T1 |
28 |
|
T3 |
21 |
|
T13 |
19 |
auto[0] |
byte_access |
10617 |
1 |
|
|
T1 |
19 |
|
T3 |
22 |
|
T13 |
4 |
auto[1] |
word_access |
9513296 |
1 |
|
|
T1 |
25032 |
|
T2 |
5000 |
|
T3 |
23782 |