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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.66 95.77 90.51 100.00 66.94 93.67 98.84 95.86


Total test records in report: 871
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T766 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2354779530 Aug 12 06:23:47 PM PDT 24 Aug 12 06:23:50 PM PDT 24 507380523 ps
T767 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.532410583 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:23 PM PDT 24 37772168 ps
T768 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.466636284 Aug 12 06:23:47 PM PDT 24 Aug 12 06:23:48 PM PDT 24 159273606 ps
T769 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1941500724 Aug 12 06:23:46 PM PDT 24 Aug 12 06:23:48 PM PDT 24 65230979 ps
T770 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3256158429 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:25 PM PDT 24 480868139 ps
T771 /workspace/coverage/cover_reg_top/27.kmac_intr_test.3813891465 Aug 12 06:23:59 PM PDT 24 Aug 12 06:24:00 PM PDT 24 20728206 ps
T772 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2549858449 Aug 12 06:24:09 PM PDT 24 Aug 12 06:24:10 PM PDT 24 18632973 ps
T773 /workspace/coverage/cover_reg_top/13.kmac_intr_test.3016151398 Aug 12 06:23:46 PM PDT 24 Aug 12 06:23:47 PM PDT 24 25092466 ps
T774 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1184885249 Aug 12 06:23:43 PM PDT 24 Aug 12 06:23:45 PM PDT 24 248593599 ps
T775 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2836314010 Aug 12 06:23:43 PM PDT 24 Aug 12 06:23:44 PM PDT 24 72792474 ps
T116 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2068664143 Aug 12 06:24:02 PM PDT 24 Aug 12 06:24:04 PM PDT 24 568229566 ps
T776 /workspace/coverage/cover_reg_top/45.kmac_intr_test.1453342108 Aug 12 06:24:00 PM PDT 24 Aug 12 06:24:01 PM PDT 24 17605295 ps
T154 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.772499350 Aug 12 06:23:27 PM PDT 24 Aug 12 06:23:32 PM PDT 24 1158930107 ps
T777 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2802259465 Aug 12 06:23:34 PM PDT 24 Aug 12 06:23:42 PM PDT 24 362208631 ps
T121 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2952164760 Aug 12 06:23:57 PM PDT 24 Aug 12 06:24:00 PM PDT 24 244147283 ps
T152 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.4128517494 Aug 12 06:23:23 PM PDT 24 Aug 12 06:23:28 PM PDT 24 242431807 ps
T778 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3430274710 Aug 12 06:23:43 PM PDT 24 Aug 12 06:23:53 PM PDT 24 29042783 ps
T779 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.375277352 Aug 12 06:23:52 PM PDT 24 Aug 12 06:23:53 PM PDT 24 61856776 ps
T132 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.927042347 Aug 12 06:23:35 PM PDT 24 Aug 12 06:23:36 PM PDT 24 98829069 ps
T780 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3602977787 Aug 12 06:23:55 PM PDT 24 Aug 12 06:23:56 PM PDT 24 32715803 ps
T781 /workspace/coverage/cover_reg_top/38.kmac_intr_test.1813599159 Aug 12 06:23:55 PM PDT 24 Aug 12 06:23:56 PM PDT 24 24699813 ps
T782 /workspace/coverage/cover_reg_top/20.kmac_intr_test.2447436213 Aug 12 06:23:50 PM PDT 24 Aug 12 06:23:51 PM PDT 24 37111765 ps
T783 /workspace/coverage/cover_reg_top/39.kmac_intr_test.2859342465 Aug 12 06:23:58 PM PDT 24 Aug 12 06:23:59 PM PDT 24 20555422 ps
T784 /workspace/coverage/cover_reg_top/47.kmac_intr_test.1401744416 Aug 12 06:24:03 PM PDT 24 Aug 12 06:24:04 PM PDT 24 31473609 ps
T785 /workspace/coverage/cover_reg_top/3.kmac_intr_test.2373088144 Aug 12 06:23:29 PM PDT 24 Aug 12 06:23:30 PM PDT 24 11125636 ps
T786 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2320847804 Aug 12 06:23:48 PM PDT 24 Aug 12 06:23:51 PM PDT 24 75244162 ps
T787 /workspace/coverage/cover_reg_top/32.kmac_intr_test.2975704100 Aug 12 06:23:58 PM PDT 24 Aug 12 06:23:59 PM PDT 24 22746746 ps
T788 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1213932785 Aug 12 06:23:47 PM PDT 24 Aug 12 06:23:50 PM PDT 24 190940973 ps
T789 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2866124085 Aug 12 06:23:40 PM PDT 24 Aug 12 06:23:42 PM PDT 24 338792100 ps
T117 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1363636020 Aug 12 06:23:54 PM PDT 24 Aug 12 06:23:59 PM PDT 24 139676292 ps
T790 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2562719205 Aug 12 06:23:38 PM PDT 24 Aug 12 06:23:40 PM PDT 24 235325009 ps
T791 /workspace/coverage/cover_reg_top/2.kmac_intr_test.3442124562 Aug 12 06:23:26 PM PDT 24 Aug 12 06:23:27 PM PDT 24 16833206 ps
T792 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1655342261 Aug 12 06:23:32 PM PDT 24 Aug 12 06:23:33 PM PDT 24 56481770 ps
T793 /workspace/coverage/cover_reg_top/22.kmac_intr_test.391484618 Aug 12 06:23:47 PM PDT 24 Aug 12 06:23:48 PM PDT 24 16730979 ps
T794 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1017961169 Aug 12 06:23:58 PM PDT 24 Aug 12 06:23:59 PM PDT 24 108152726 ps
T795 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.3515745354 Aug 12 06:23:26 PM PDT 24 Aug 12 06:23:29 PM PDT 24 129132745 ps
T796 /workspace/coverage/cover_reg_top/15.kmac_intr_test.4162083453 Aug 12 06:23:52 PM PDT 24 Aug 12 06:23:53 PM PDT 24 171032240 ps
T161 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2282271993 Aug 12 06:23:49 PM PDT 24 Aug 12 06:23:54 PM PDT 24 833724008 ps
T155 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3707091622 Aug 12 06:23:39 PM PDT 24 Aug 12 06:23:42 PM PDT 24 133724719 ps
T797 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1465693454 Aug 12 06:23:31 PM PDT 24 Aug 12 06:23:32 PM PDT 24 12866899 ps
T120 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.301544404 Aug 12 06:23:24 PM PDT 24 Aug 12 06:23:27 PM PDT 24 31802388 ps
T798 /workspace/coverage/cover_reg_top/46.kmac_intr_test.1424908859 Aug 12 06:23:58 PM PDT 24 Aug 12 06:23:59 PM PDT 24 22386241 ps
T799 /workspace/coverage/cover_reg_top/17.kmac_intr_test.2972637739 Aug 12 06:23:37 PM PDT 24 Aug 12 06:23:38 PM PDT 24 20179364 ps
T800 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.725214081 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:14 PM PDT 24 269933816 ps
T801 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3302151731 Aug 12 06:23:33 PM PDT 24 Aug 12 06:23:48 PM PDT 24 1172355381 ps
T802 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3211749467 Aug 12 06:24:08 PM PDT 24 Aug 12 06:24:11 PM PDT 24 789370845 ps
T803 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.4072462345 Aug 12 06:23:25 PM PDT 24 Aug 12 06:23:26 PM PDT 24 15241473 ps
T804 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1205897907 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:25 PM PDT 24 373670056 ps
T805 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.264012931 Aug 12 06:23:49 PM PDT 24 Aug 12 06:23:52 PM PDT 24 669240283 ps
T806 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4108691418 Aug 12 06:23:41 PM PDT 24 Aug 12 06:23:44 PM PDT 24 89554898 ps
T807 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2779923222 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:24 PM PDT 24 272958962 ps
T808 /workspace/coverage/cover_reg_top/25.kmac_intr_test.2125162909 Aug 12 06:23:56 PM PDT 24 Aug 12 06:23:57 PM PDT 24 28165059 ps
T809 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3080934310 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:14 PM PDT 24 111235506 ps
T158 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1973382825 Aug 12 06:23:56 PM PDT 24 Aug 12 06:23:59 PM PDT 24 809241112 ps
T810 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.823169190 Aug 12 06:23:29 PM PDT 24 Aug 12 06:23:33 PM PDT 24 149349522 ps
T811 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.829408396 Aug 12 06:23:42 PM PDT 24 Aug 12 06:23:44 PM PDT 24 96864835 ps
T812 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1229888515 Aug 12 06:23:28 PM PDT 24 Aug 12 06:23:43 PM PDT 24 1166917839 ps
T813 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3448316495 Aug 12 06:23:59 PM PDT 24 Aug 12 06:24:01 PM PDT 24 229358723 ps
T814 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.772492688 Aug 12 06:23:41 PM PDT 24 Aug 12 06:23:42 PM PDT 24 79889659 ps
T815 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1129269823 Aug 12 06:23:45 PM PDT 24 Aug 12 06:23:46 PM PDT 24 20488712 ps
T816 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3998719914 Aug 12 06:23:47 PM PDT 24 Aug 12 06:23:49 PM PDT 24 32146420 ps
T817 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3562076902 Aug 12 06:23:30 PM PDT 24 Aug 12 06:23:48 PM PDT 24 4040933772 ps
T818 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3113231456 Aug 12 06:23:43 PM PDT 24 Aug 12 06:23:44 PM PDT 24 99701084 ps
T819 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1465774241 Aug 12 06:23:31 PM PDT 24 Aug 12 06:23:36 PM PDT 24 222073802 ps
T157 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3353174524 Aug 12 06:23:50 PM PDT 24 Aug 12 06:23:54 PM PDT 24 825591008 ps
T820 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1092970507 Aug 12 06:23:31 PM PDT 24 Aug 12 06:23:36 PM PDT 24 380623765 ps
T821 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2707098749 Aug 12 06:23:38 PM PDT 24 Aug 12 06:23:39 PM PDT 24 49687761 ps
T822 /workspace/coverage/cover_reg_top/33.kmac_intr_test.4176963162 Aug 12 06:23:56 PM PDT 24 Aug 12 06:23:57 PM PDT 24 72886420 ps
T823 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1286717706 Aug 12 06:23:54 PM PDT 24 Aug 12 06:23:55 PM PDT 24 62288163 ps
T824 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1171883838 Aug 12 06:23:42 PM PDT 24 Aug 12 06:23:44 PM PDT 24 25651053 ps
T825 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.264896736 Aug 12 06:23:35 PM PDT 24 Aug 12 06:23:37 PM PDT 24 250929601 ps
T826 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3050157377 Aug 12 06:23:45 PM PDT 24 Aug 12 06:23:47 PM PDT 24 36923282 ps
T118 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3095543158 Aug 12 06:23:20 PM PDT 24 Aug 12 06:23:22 PM PDT 24 229856480 ps
T827 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1639630594 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:13 PM PDT 24 126298977 ps
T828 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1060558117 Aug 12 06:23:58 PM PDT 24 Aug 12 06:24:01 PM PDT 24 200940110 ps
T829 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1770607290 Aug 12 06:23:43 PM PDT 24 Aug 12 06:23:48 PM PDT 24 1129123894 ps
T830 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3299725426 Aug 12 06:23:45 PM PDT 24 Aug 12 06:23:46 PM PDT 24 25461827 ps
T831 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3138783126 Aug 12 06:23:43 PM PDT 24 Aug 12 06:24:03 PM PDT 24 4612763967 ps
T832 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2903285284 Aug 12 06:23:27 PM PDT 24 Aug 12 06:23:29 PM PDT 24 39552574 ps
T833 /workspace/coverage/cover_reg_top/36.kmac_intr_test.1850948017 Aug 12 06:24:03 PM PDT 24 Aug 12 06:24:04 PM PDT 24 31142931 ps
T834 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1703317300 Aug 12 06:23:31 PM PDT 24 Aug 12 06:23:33 PM PDT 24 120471873 ps
T835 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3814708031 Aug 12 06:23:36 PM PDT 24 Aug 12 06:23:37 PM PDT 24 22083048 ps
T836 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.450605879 Aug 12 06:23:49 PM PDT 24 Aug 12 06:23:51 PM PDT 24 50359353 ps
T837 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.521110455 Aug 12 06:23:21 PM PDT 24 Aug 12 06:23:22 PM PDT 24 25826132 ps
T838 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1992024364 Aug 12 06:23:24 PM PDT 24 Aug 12 06:23:25 PM PDT 24 21347965 ps
T839 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.401268242 Aug 12 06:23:30 PM PDT 24 Aug 12 06:23:32 PM PDT 24 62970743 ps
T840 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2153250590 Aug 12 06:23:48 PM PDT 24 Aug 12 06:23:52 PM PDT 24 330924802 ps
T841 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2423624891 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:14 PM PDT 24 29663781 ps
T842 /workspace/coverage/cover_reg_top/10.kmac_intr_test.227364761 Aug 12 06:23:35 PM PDT 24 Aug 12 06:23:36 PM PDT 24 26429958 ps
T843 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.331722467 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:25 PM PDT 24 420142824 ps
T844 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2446272015 Aug 12 06:24:06 PM PDT 24 Aug 12 06:24:08 PM PDT 24 37913235 ps
T845 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.925589003 Aug 12 06:23:34 PM PDT 24 Aug 12 06:23:35 PM PDT 24 77555326 ps
T846 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3069103035 Aug 12 06:24:00 PM PDT 24 Aug 12 06:24:02 PM PDT 24 95912348 ps
T847 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3191303299 Aug 12 06:23:50 PM PDT 24 Aug 12 06:23:53 PM PDT 24 129584745 ps
T848 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3779972388 Aug 12 06:23:45 PM PDT 24 Aug 12 06:23:48 PM PDT 24 1002526971 ps
T849 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2371222786 Aug 12 06:23:48 PM PDT 24 Aug 12 06:23:52 PM PDT 24 138674327 ps
T850 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.486803047 Aug 12 06:24:15 PM PDT 24 Aug 12 06:24:16 PM PDT 24 38541545 ps
T851 /workspace/coverage/cover_reg_top/34.kmac_intr_test.4211586854 Aug 12 06:23:52 PM PDT 24 Aug 12 06:23:53 PM PDT 24 38926899 ps
T852 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.925298410 Aug 12 06:23:32 PM PDT 24 Aug 12 06:23:34 PM PDT 24 27868698 ps
T853 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1537723633 Aug 12 06:23:37 PM PDT 24 Aug 12 06:23:39 PM PDT 24 123903410 ps
T854 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1078969203 Aug 12 06:23:25 PM PDT 24 Aug 12 06:23:34 PM PDT 24 1513515779 ps
T855 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3608370009 Aug 12 06:23:41 PM PDT 24 Aug 12 06:23:42 PM PDT 24 49380908 ps
T856 /workspace/coverage/cover_reg_top/11.kmac_intr_test.139990569 Aug 12 06:23:46 PM PDT 24 Aug 12 06:23:47 PM PDT 24 28817536 ps
T159 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1601578560 Aug 12 06:23:51 PM PDT 24 Aug 12 06:23:54 PM PDT 24 732567593 ps
T857 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2619634091 Aug 12 06:23:42 PM PDT 24 Aug 12 06:23:43 PM PDT 24 27434268 ps
T858 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3504686876 Aug 12 06:23:48 PM PDT 24 Aug 12 06:23:49 PM PDT 24 19079234 ps
T156 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2246315535 Aug 12 06:23:43 PM PDT 24 Aug 12 06:23:46 PM PDT 24 133012482 ps
T859 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1036551675 Aug 12 06:23:49 PM PDT 24 Aug 12 06:23:51 PM PDT 24 99122641 ps
T860 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1355899570 Aug 12 06:23:17 PM PDT 24 Aug 12 06:23:19 PM PDT 24 50656110 ps
T160 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1263834823 Aug 12 06:23:30 PM PDT 24 Aug 12 06:23:33 PM PDT 24 185424340 ps
T861 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2731172196 Aug 12 06:23:46 PM PDT 24 Aug 12 06:23:47 PM PDT 24 18358599 ps
T862 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1297942212 Aug 12 06:23:24 PM PDT 24 Aug 12 06:23:25 PM PDT 24 11288969 ps
T863 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3287362276 Aug 12 06:23:38 PM PDT 24 Aug 12 06:23:41 PM PDT 24 140478030 ps
T864 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1738875182 Aug 12 06:23:28 PM PDT 24 Aug 12 06:23:37 PM PDT 24 394700617 ps
T865 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.895462031 Aug 12 06:23:44 PM PDT 24 Aug 12 06:23:45 PM PDT 24 41897907 ps
T866 /workspace/coverage/cover_reg_top/31.kmac_intr_test.4028979052 Aug 12 06:23:45 PM PDT 24 Aug 12 06:23:46 PM PDT 24 11103726 ps
T867 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1860748881 Aug 12 06:24:05 PM PDT 24 Aug 12 06:24:07 PM PDT 24 477306987 ps
T868 /workspace/coverage/cover_reg_top/29.kmac_intr_test.3844366803 Aug 12 06:23:56 PM PDT 24 Aug 12 06:23:57 PM PDT 24 12498043 ps
T869 /workspace/coverage/cover_reg_top/44.kmac_intr_test.3505756512 Aug 12 06:24:04 PM PDT 24 Aug 12 06:24:05 PM PDT 24 39010991 ps
T870 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1269491042 Aug 12 06:23:26 PM PDT 24 Aug 12 06:23:27 PM PDT 24 58695543 ps
T871 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2628211739 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:13 PM PDT 24 14968033 ps

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.2022785591
Short name T1
Test name
Test status
Simulation time 19863897737 ps
CPU time 197.82 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 06:30:05 PM PDT 24
Peak memory 301112 kb
Host smart-0b4c165e-ee45-4c19-a907-ed85d9de3afd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022785591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.2022785591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3434783722
Short name T103
Test name
Test status
Simulation time 248665542 ps
CPU time 5.03 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 215440 kb
Host smart-4475459b-cca2-4e0c-9332-e486a16477b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434783722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.34347
83722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.2932507370
Short name T4
Test name
Test status
Simulation time 44924704 ps
CPU time 1.21 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:26:59 PM PDT 24
Peak memory 218892 kb
Host smart-9f4fa43b-5e41-41e6-8962-142a02ac705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932507370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2932507370 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_stress_all.2152633638
Short name T22
Test name
Test status
Simulation time 10158145673 ps
CPU time 776.71 seconds
Started Aug 12 06:27:27 PM PDT 24
Finished Aug 12 06:40:24 PM PDT 24
Peak memory 607912 kb
Host smart-71436427-25c6-4c1a-ac67-b3b60c5de351
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2152633638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2152633638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.3961079524
Short name T10
Test name
Test status
Simulation time 40552198442 ps
CPU time 74.74 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:27:31 PM PDT 24
Peak memory 274712 kb
Host smart-18d51d8c-0dbf-4235-bf59-d89c7c4037a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961079524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3961079524 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/24.kmac_key_error.2143828194
Short name T15
Test name
Test status
Simulation time 809266618 ps
CPU time 4.68 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:27:24 PM PDT 24
Peak memory 217592 kb
Host smart-e01e5e42-bf79-4d29-add1-b55b1949d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143828194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2143828194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2831073120
Short name T7
Test name
Test status
Simulation time 42871449 ps
CPU time 1.38 seconds
Started Aug 12 06:28:00 PM PDT 24
Finished Aug 12 06:28:01 PM PDT 24
Peak memory 217796 kb
Host smart-eef9984c-c281-4a7e-9218-9dd944000c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831073120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2831073120 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_error.770191764
Short name T3
Test name
Test status
Simulation time 24220656830 ps
CPU time 276.04 seconds
Started Aug 12 06:26:25 PM PDT 24
Finished Aug 12 06:31:01 PM PDT 24
Peak memory 482680 kb
Host smart-294f8238-2f0b-4c55-b50a-b796ca8ffd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770191764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.770191764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3832266873
Short name T90
Test name
Test status
Simulation time 43649246 ps
CPU time 1.3 seconds
Started Aug 12 06:23:46 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 215584 kb
Host smart-55099f53-3444-4427-aff8-9bd6931275d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832266873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.3832266873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1171007341
Short name T109
Test name
Test status
Simulation time 243701973 ps
CPU time 2.91 seconds
Started Aug 12 06:23:40 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 215160 kb
Host smart-9f0df38a-0cf7-41e2-837f-9b16ac80e8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171007341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1171007341 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.4015395257
Short name T147
Test name
Test status
Simulation time 44987436 ps
CPU time 0.79 seconds
Started Aug 12 06:23:53 PM PDT 24
Finished Aug 12 06:23:54 PM PDT 24
Peak memory 206616 kb
Host smart-87882e63-ebb2-461d-b6ac-4d8b7903c5eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015395257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.4015395257 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.187671585
Short name T8
Test name
Test status
Simulation time 177593168 ps
CPU time 1.24 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:27:03 PM PDT 24
Peak memory 217812 kb
Host smart-0c64d06d-f98a-4ae0-b5a4-bc144932fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187671585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.187671585 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.1467690484
Short name T51
Test name
Test status
Simulation time 51600748 ps
CPU time 1.16 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:27:00 PM PDT 24
Peak memory 217036 kb
Host smart-6a0559e4-ae36-4c52-9b36-0deccca12a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467690484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1467690484 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1620370214
Short name T264
Test name
Test status
Simulation time 25992416 ps
CPU time 0.77 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:26:58 PM PDT 24
Peak memory 204520 kb
Host smart-81880df0-f7c6-4404-97b4-c0a3d51e20ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620370214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1620370214 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.927042347
Short name T132
Test name
Test status
Simulation time 98829069 ps
CPU time 1.23 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 214996 kb
Host smart-d1762624-c379-4651-a95a-9bf0a4ff17a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927042347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial
_access.927042347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/43.kmac_stress_all.3819900258
Short name T129
Test name
Test status
Simulation time 19260630600 ps
CPU time 1415.37 seconds
Started Aug 12 06:28:00 PM PDT 24
Finished Aug 12 06:51:36 PM PDT 24
Peak memory 706916 kb
Host smart-16a56afa-4e40-4931-9874-a273c13e75a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3819900258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3819900258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_stress_all.1428775640
Short name T76
Test name
Test status
Simulation time 19162050034 ps
CPU time 1722.64 seconds
Started Aug 12 06:26:32 PM PDT 24
Finished Aug 12 06:55:15 PM PDT 24
Peak memory 591680 kb
Host smart-6712dcc1-0784-4003-84fb-5fd8cd18da1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1428775640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1428775640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.772499350
Short name T154
Test name
Test status
Simulation time 1158930107 ps
CPU time 5.22 seconds
Started Aug 12 06:23:27 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 215012 kb
Host smart-f489ac4c-54aa-4efd-a9db-4782f8d26315
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772499350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.77249
9350 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2728725714
Short name T97
Test name
Test status
Simulation time 48673966 ps
CPU time 2.55 seconds
Started Aug 12 06:23:55 PM PDT 24
Finished Aug 12 06:23:57 PM PDT 24
Peak memory 215564 kb
Host smart-32bcd0e3-a442-4512-a510-255af136ffc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728725714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2728725714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2620112963
Short name T113
Test name
Test status
Simulation time 15286560 ps
CPU time 0.76 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 206528 kb
Host smart-12c5c8b9-c8c5-40ab-9634-312269ca8900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620112963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2620112963 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2153250590
Short name T840
Test name
Test status
Simulation time 330924802 ps
CPU time 4.43 seconds
Started Aug 12 06:23:48 PM PDT 24
Finished Aug 12 06:23:52 PM PDT 24
Peak memory 215052 kb
Host smart-91cf4cc4-962f-43bd-a7e9-b073d8684a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153250590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2153250590 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/default/13.kmac_stress_all.246465107
Short name T99
Test name
Test status
Simulation time 85656635718 ps
CPU time 436.43 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:34:16 PM PDT 24
Peak memory 318788 kb
Host smart-f15e2134-7958-4308-ac28-b9c2aa0e2f58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=246465107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.246465107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_error.2011447880
Short name T29
Test name
Test status
Simulation time 3238709797 ps
CPU time 218.05 seconds
Started Aug 12 06:27:29 PM PDT 24
Finished Aug 12 06:31:07 PM PDT 24
Peak memory 331508 kb
Host smart-0c1f02d1-65f8-46a2-8d81-14699caab5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011447880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2011447880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.1660798814
Short name T472
Test name
Test status
Simulation time 9915931038 ps
CPU time 25.64 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:27:08 PM PDT 24
Peak memory 218580 kb
Host smart-53f0b653-73e3-4d8f-a179-bafe20e67bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660798814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1660798814 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/32.kmac_sideload.547659060
Short name T167
Test name
Test status
Simulation time 25250216817 ps
CPU time 377.05 seconds
Started Aug 12 06:27:32 PM PDT 24
Finished Aug 12 06:33:50 PM PDT 24
Peak memory 564212 kb
Host smart-d4290181-dac5-4275-a4a8-5a6dfb6e5b46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547659060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.547659060 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.4128517494
Short name T152
Test name
Test status
Simulation time 242431807 ps
CPU time 4.59 seconds
Started Aug 12 06:23:23 PM PDT 24
Finished Aug 12 06:23:28 PM PDT 24
Peak memory 215116 kb
Host smart-f4aa0a77-7418-4aea-a897-eb1cc28d65fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128517494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.41285
17494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3707091622
Short name T155
Test name
Test status
Simulation time 133724719 ps
CPU time 2.83 seconds
Started Aug 12 06:23:39 PM PDT 24
Finished Aug 12 06:23:42 PM PDT 24
Peak memory 223192 kb
Host smart-cab0eade-21a0-4115-812a-259ce6181448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707091622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3707
091622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.kmac_stress_all.282988101
Short name T78
Test name
Test status
Simulation time 221186866786 ps
CPU time 1501.79 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:51:59 PM PDT 24
Peak memory 1181004 kb
Host smart-6e0501bd-7768-4560-a44e-f27fbd603020
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=282988101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.282988101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3322263162
Short name T107
Test name
Test status
Simulation time 23638631 ps
CPU time 1.39 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:30 PM PDT 24
Peak memory 215196 kb
Host smart-0a8c7245-bf06-4d11-b972-b16a95f52b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322263162 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3322263162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1189730976
Short name T89
Test name
Test status
Simulation time 95780293 ps
CPU time 1.08 seconds
Started Aug 12 06:23:30 PM PDT 24
Finished Aug 12 06:23:31 PM PDT 24
Peak memory 215644 kb
Host smart-3b079827-2943-482c-be51-11b76976c238
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189730976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.1189730976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.725214081
Short name T800
Test name
Test status
Simulation time 269933816 ps
CPU time 8.05 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 206884 kb
Host smart-b11c705c-64dc-420b-a56e-9d8d430888e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725214081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.72521408
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3562076902
Short name T817
Test name
Test status
Simulation time 4040933772 ps
CPU time 17.95 seconds
Started Aug 12 06:23:30 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 206928 kb
Host smart-90c35bf4-cbae-4a10-8246-8a0f4e3c7c1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562076902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3562076
902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.925589003
Short name T845
Test name
Test status
Simulation time 77555326 ps
CPU time 0.98 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 206608 kb
Host smart-b941acd9-2208-473d-9fdd-09b99b8e1ab5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925589003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.92558900
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.155007939
Short name T48
Test name
Test status
Simulation time 81275611 ps
CPU time 1.58 seconds
Started Aug 12 06:23:36 PM PDT 24
Finished Aug 12 06:23:38 PM PDT 24
Peak memory 223340 kb
Host smart-e8794b1a-afa2-44a0-bc06-f7b263a39796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155007939 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.155007939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.4072462345
Short name T803
Test name
Test status
Simulation time 15241473 ps
CPU time 0.9 seconds
Started Aug 12 06:23:25 PM PDT 24
Finished Aug 12 06:23:26 PM PDT 24
Peak memory 206700 kb
Host smart-0eb3e798-7667-479e-898f-a2e47921b670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072462345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.4072462345 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2628211739
Short name T871
Test name
Test status
Simulation time 14968033 ps
CPU time 0.74 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 206600 kb
Host smart-12a86217-aecc-49e3-8b31-7000ae0a09ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628211739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2628211739 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3113231456
Short name T818
Test name
Test status
Simulation time 99701084 ps
CPU time 1.26 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 215060 kb
Host smart-5ea54167-786f-4db3-9a56-193dc9ff7555
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113231456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3113231456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1465693454
Short name T797
Test name
Test status
Simulation time 12866899 ps
CPU time 0.7 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 206620 kb
Host smart-73e71cbf-a836-4499-b903-f957270a3b67
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465693454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1465693454
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1680107839
Short name T138
Test name
Test status
Simulation time 61522229 ps
CPU time 1.6 seconds
Started Aug 12 06:23:33 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 215108 kb
Host smart-815cce65-f566-4f95-8bf2-3ba66c18d897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680107839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.1680107839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1639630594
Short name T827
Test name
Test status
Simulation time 126298977 ps
CPU time 1.21 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 215636 kb
Host smart-9648e7d1-67b6-48ee-a874-c0ec88c056b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639630594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.1639630594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1355899570
Short name T860
Test name
Test status
Simulation time 50656110 ps
CPU time 2.34 seconds
Started Aug 12 06:23:17 PM PDT 24
Finished Aug 12 06:23:19 PM PDT 24
Peak memory 223744 kb
Host smart-5155c99a-b256-412d-81b6-d85cbb1f3a0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355899570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.1355899570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2423624891
Short name T841
Test name
Test status
Simulation time 29663781 ps
CPU time 1.56 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 215048 kb
Host smart-5223355e-b4b9-482d-9542-a53587f4dc4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423624891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2423624891 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1078969203
Short name T854
Test name
Test status
Simulation time 1513515779 ps
CPU time 9.08 seconds
Started Aug 12 06:23:25 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 215104 kb
Host smart-d6db9ca7-f9dd-4606-8f49-4828ea042981
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078969203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1078969
203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.930857147
Short name T742
Test name
Test status
Simulation time 155091628 ps
CPU time 7.7 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:21 PM PDT 24
Peak memory 206876 kb
Host smart-7316228c-1d4e-4653-bf60-3bcbca4a5fc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930857147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.93085714
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3347013124
Short name T733
Test name
Test status
Simulation time 22661190 ps
CPU time 0.94 seconds
Started Aug 12 06:23:15 PM PDT 24
Finished Aug 12 06:23:16 PM PDT 24
Peak memory 206668 kb
Host smart-68bb4752-d564-4942-baa3-8a73316b59a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347013124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3347013
124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.779377048
Short name T757
Test name
Test status
Simulation time 149105669 ps
CPU time 1.54 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:24 PM PDT 24
Peak memory 215164 kb
Host smart-bc16e031-6007-46e1-94cd-e3e71466fed7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779377048 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.779377048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.333070735
Short name T135
Test name
Test status
Simulation time 44579111 ps
CPU time 0.93 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 206668 kb
Host smart-7678d101-416c-41e3-9626-9b211b9c3f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333070735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.333070735 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.1037039359
Short name T730
Test name
Test status
Simulation time 21306872 ps
CPU time 0.74 seconds
Started Aug 12 06:23:17 PM PDT 24
Finished Aug 12 06:23:18 PM PDT 24
Peak memory 206588 kb
Host smart-e828220d-c2e0-4290-8ce2-d59a6b772007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037039359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1037039359 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3496295851
Short name T755
Test name
Test status
Simulation time 128911769 ps
CPU time 1.35 seconds
Started Aug 12 06:23:09 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 215076 kb
Host smart-fad28792-a495-4ba7-96c2-cd16f3213a22
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496295851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.3496295851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1992024364
Short name T838
Test name
Test status
Simulation time 21347965 ps
CPU time 0.69 seconds
Started Aug 12 06:23:24 PM PDT 24
Finished Aug 12 06:23:25 PM PDT 24
Peak memory 206584 kb
Host smart-66c05450-8114-4404-bf08-bce305b046fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992024364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1992024364
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1205897907
Short name T804
Test name
Test status
Simulation time 373670056 ps
CPU time 2.5 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:25 PM PDT 24
Peak memory 215660 kb
Host smart-bf63593e-ec45-4d5b-8c2e-39cf22c2cd11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205897907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.1205897907 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3080934310
Short name T809
Test name
Test status
Simulation time 111235506 ps
CPU time 1 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 215520 kb
Host smart-37c80e8f-ff47-42b3-9175-8223a4978964
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080934310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3080934310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.103486726
Short name T743
Test name
Test status
Simulation time 45548807 ps
CPU time 2.3 seconds
Started Aug 12 06:23:32 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 215616 kb
Host smart-e4d64048-7ccf-4e31-bb8e-34323a1a909c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103486726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_
shadow_reg_errors_with_csr_rw.103486726 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.2295517174
Short name T115
Test name
Test status
Simulation time 156758670 ps
CPU time 2.66 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 215184 kb
Host smart-e873f9be-969d-428b-a4a5-6a38be45c911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295517174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2295517174 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2246315535
Short name T156
Test name
Test status
Simulation time 133012482 ps
CPU time 2.66 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:46 PM PDT 24
Peak memory 215048 kb
Host smart-330744dd-313b-44c0-a89a-780f9291a43f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246315535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.22463
15535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2803098892
Short name T140
Test name
Test status
Simulation time 112113165 ps
CPU time 1.11 seconds
Started Aug 12 06:23:45 PM PDT 24
Finished Aug 12 06:23:46 PM PDT 24
Peak memory 206912 kb
Host smart-bcb401cc-9863-4a47-8b29-b21fc6657742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803098892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2803098892 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.227364761
Short name T842
Test name
Test status
Simulation time 26429958 ps
CPU time 0.76 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 206652 kb
Host smart-a7466c4c-b796-47ac-bbe3-7a046af43a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227364761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.227364761 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3779972388
Short name T848
Test name
Test status
Simulation time 1002526971 ps
CPU time 2.51 seconds
Started Aug 12 06:23:45 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 215336 kb
Host smart-4cc1682c-6bab-4c0c-8fbc-4b14694de674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779972388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3779972388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.450605879
Short name T836
Test name
Test status
Simulation time 50359353 ps
CPU time 1.19 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 215672 kb
Host smart-0f3e8282-cec1-4308-ac92-a4034d182b63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450605879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_
errors.450605879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4108691418
Short name T806
Test name
Test status
Simulation time 89554898 ps
CPU time 2.48 seconds
Started Aug 12 06:23:41 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 223372 kb
Host smart-58b98de9-3d03-4414-8ebd-ebe6764457a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108691418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.4108691418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2429877299
Short name T119
Test name
Test status
Simulation time 163759786 ps
CPU time 2.47 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:38 PM PDT 24
Peak memory 215168 kb
Host smart-4ffced9e-0a46-420c-9068-bfe28de69bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429877299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2429877299 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2707098749
Short name T821
Test name
Test status
Simulation time 49687761 ps
CPU time 1.65 seconds
Started Aug 12 06:23:38 PM PDT 24
Finished Aug 12 06:23:39 PM PDT 24
Peak memory 215128 kb
Host smart-5546499e-49c1-4f93-8171-7755460b149a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707098749 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2707098749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2455135731
Short name T747
Test name
Test status
Simulation time 24512457 ps
CPU time 0.89 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 206716 kb
Host smart-e9971f0d-0f0b-4935-861c-4996c0ebaf57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455135731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2455135731 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.139990569
Short name T856
Test name
Test status
Simulation time 28817536 ps
CPU time 0.77 seconds
Started Aug 12 06:23:46 PM PDT 24
Finished Aug 12 06:23:47 PM PDT 24
Peak memory 206652 kb
Host smart-a87bfef0-9ce2-4138-b774-0bebc2b737cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139990569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.139990569 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1672163338
Short name T764
Test name
Test status
Simulation time 288998112 ps
CPU time 1.49 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 215432 kb
Host smart-2eebf16e-0196-4d46-ae0b-9b7a6491a9db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672163338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1672163338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2981662993
Short name T92
Test name
Test status
Simulation time 82107367 ps
CPU time 2.25 seconds
Started Aug 12 06:23:41 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 215628 kb
Host smart-4b828ecb-e2f7-4878-a37a-95704bc3135b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981662993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.2981662993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.4246611173
Short name T108
Test name
Test status
Simulation time 49012408 ps
CPU time 2.74 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:37 PM PDT 24
Peak memory 215164 kb
Host smart-24bfeb9d-d04d-4eb5-9dc0-221f3c56e927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246611173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.4246611173 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2836314010
Short name T775
Test name
Test status
Simulation time 72792474 ps
CPU time 1.47 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 215064 kb
Host smart-cd701ce5-6b4a-4e1d-8ffa-742b41a99c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836314010 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2836314010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3299725426
Short name T830
Test name
Test status
Simulation time 25461827 ps
CPU time 0.91 seconds
Started Aug 12 06:23:45 PM PDT 24
Finished Aug 12 06:23:46 PM PDT 24
Peak memory 206720 kb
Host smart-a8bf7c90-d510-484d-be2a-10d0bc99d17a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299725426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3299725426 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.657387518
Short name T739
Test name
Test status
Simulation time 35161446 ps
CPU time 0.76 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 206620 kb
Host smart-973b0863-0b80-49f3-bf85-9ae391af258d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657387518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.657387518 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1356758790
Short name T754
Test name
Test status
Simulation time 90061566 ps
CPU time 2.21 seconds
Started Aug 12 06:23:50 PM PDT 24
Finished Aug 12 06:23:52 PM PDT 24
Peak memory 215376 kb
Host smart-300ed6bc-2631-49dd-b67d-244ab0bd381b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356758790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.1356758790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.895462031
Short name T865
Test name
Test status
Simulation time 41897907 ps
CPU time 1.13 seconds
Started Aug 12 06:23:44 PM PDT 24
Finished Aug 12 06:23:45 PM PDT 24
Peak memory 215688 kb
Host smart-3e60917b-7f1d-42a4-b97f-c4251b0622be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895462031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_
errors.895462031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2742900912
Short name T95
Test name
Test status
Simulation time 196613950 ps
CPU time 2.75 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:24:01 PM PDT 24
Peak memory 223612 kb
Host smart-80a9885f-d42c-4d50-9e6d-3f4e8cff5582
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742900912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.2742900912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2371222786
Short name T849
Test name
Test status
Simulation time 138674327 ps
CPU time 3.67 seconds
Started Aug 12 06:23:48 PM PDT 24
Finished Aug 12 06:23:52 PM PDT 24
Peak memory 215144 kb
Host smart-2a5aabbf-f95a-4946-914d-bdf2a05e6cf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371222786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2371222786 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1601578560
Short name T159
Test name
Test status
Simulation time 732567593 ps
CPU time 2.45 seconds
Started Aug 12 06:23:51 PM PDT 24
Finished Aug 12 06:23:54 PM PDT 24
Peak memory 206864 kb
Host smart-50ac9028-019b-42e1-86b1-f401d96ec29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601578560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1601
578560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2377004267
Short name T746
Test name
Test status
Simulation time 44255099 ps
CPU time 1.61 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 215280 kb
Host smart-e8ca0f01-8629-4bde-adc6-0ca5c388a6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377004267 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2377004267 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1349477202
Short name T741
Test name
Test status
Simulation time 45927408 ps
CPU time 0.92 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 206636 kb
Host smart-d32e8dd8-8ba1-4e5e-a96f-c20957cedc37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349477202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1349477202 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.3016151398
Short name T773
Test name
Test status
Simulation time 25092466 ps
CPU time 0.75 seconds
Started Aug 12 06:23:46 PM PDT 24
Finished Aug 12 06:23:47 PM PDT 24
Peak memory 206536 kb
Host smart-bbf6786e-56dc-41df-8502-cf00db441cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016151398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3016151398 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3069103035
Short name T846
Test name
Test status
Simulation time 95912348 ps
CPU time 1.53 seconds
Started Aug 12 06:24:00 PM PDT 24
Finished Aug 12 06:24:02 PM PDT 24
Peak memory 215312 kb
Host smart-118605cb-8f28-4039-8202-a22cf2f91080
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069103035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3069103035 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3998719914
Short name T816
Test name
Test status
Simulation time 32146420 ps
CPU time 1.14 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:49 PM PDT 24
Peak memory 215644 kb
Host smart-ab119350-4d91-4bfc-b2cc-2b8a06f1d4f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998719914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3998719914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2354779530
Short name T766
Test name
Test status
Simulation time 507380523 ps
CPU time 2.68 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:50 PM PDT 24
Peak memory 215624 kb
Host smart-e64ff38e-8742-4eed-a594-34c241ae7749
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354779530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2354779530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3135592330
Short name T111
Test name
Test status
Simulation time 66563137 ps
CPU time 1.74 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 215196 kb
Host smart-46e77b48-7c40-4c52-8177-79bb1f6f9785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135592330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3135592330 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3047428535
Short name T756
Test name
Test status
Simulation time 77451661 ps
CPU time 2.24 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:23:55 PM PDT 24
Peak memory 215132 kb
Host smart-a7f369ad-250e-4d9e-bede-1349de6684f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047428535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3047
428535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.292680141
Short name T126
Test name
Test status
Simulation time 206237850 ps
CPU time 1.68 seconds
Started Aug 12 06:23:46 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 216164 kb
Host smart-819f8ff2-871e-47d2-b3f4-8a1897f50a08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292680141 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.292680141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1073941860
Short name T724
Test name
Test status
Simulation time 22838132 ps
CPU time 0.99 seconds
Started Aug 12 06:23:45 PM PDT 24
Finished Aug 12 06:23:52 PM PDT 24
Peak memory 206848 kb
Host smart-2e977689-9a9b-4f8e-b33b-428ef847cd88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073941860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1073941860 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3337457776
Short name T753
Test name
Test status
Simulation time 38246070 ps
CPU time 0.76 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 206532 kb
Host smart-e1f23b42-d995-47bb-b8da-8cd995616c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337457776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3337457776 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3401085601
Short name T728
Test name
Test status
Simulation time 39778176 ps
CPU time 2.23 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:58 PM PDT 24
Peak memory 214988 kb
Host smart-38e63a6b-c31b-4f92-875a-120720d6353e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401085601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.3401085601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.466636284
Short name T768
Test name
Test status
Simulation time 159273606 ps
CPU time 1.28 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 215548 kb
Host smart-5ac09755-b587-4263-aea6-4221c59ebf70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466636284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_
errors.466636284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1213932785
Short name T788
Test name
Test status
Simulation time 190940973 ps
CPU time 2.57 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:50 PM PDT 24
Peak memory 215688 kb
Host smart-586a4c97-d09c-4fc4-97cc-4fdfb773220d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213932785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.1213932785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2068664143
Short name T116
Test name
Test status
Simulation time 568229566 ps
CPU time 2.09 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 215096 kb
Host smart-4f91a788-aee9-43b5-b042-5247e4066a76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068664143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2068664143 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.146774182
Short name T745
Test name
Test status
Simulation time 179027527 ps
CPU time 4.1 seconds
Started Aug 12 06:23:57 PM PDT 24
Finished Aug 12 06:24:02 PM PDT 24
Peak memory 206888 kb
Host smart-059f478f-39e2-4a19-bf94-3cf67b159af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146774182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.14677
4182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1184885249
Short name T774
Test name
Test status
Simulation time 248593599 ps
CPU time 2.47 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:45 PM PDT 24
Peak memory 216828 kb
Host smart-9fbecc33-8e10-4730-a6ff-3b8784c163d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184885249 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1184885249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2619634091
Short name T857
Test name
Test status
Simulation time 27434268 ps
CPU time 1.1 seconds
Started Aug 12 06:23:42 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 215100 kb
Host smart-a009b6d7-2807-4680-b07d-23dc220e16e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619634091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2619634091 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.4162083453
Short name T796
Test name
Test status
Simulation time 171032240 ps
CPU time 0.82 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 206616 kb
Host smart-b32b1595-2c0a-4b85-8b0e-4b2c01a4c6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162083453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4162083453 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1036551675
Short name T859
Test name
Test status
Simulation time 99122641 ps
CPU time 1.58 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 215080 kb
Host smart-4f09ebaa-cc77-484f-babb-a78661445893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036551675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1036551675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2373284499
Short name T760
Test name
Test status
Simulation time 57476640 ps
CPU time 1.57 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:49 PM PDT 24
Peak memory 215612 kb
Host smart-abec667c-cba5-4a22-af82-e888d020d9f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373284499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2373284499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3726811164
Short name T734
Test name
Test status
Simulation time 153521135 ps
CPU time 2.15 seconds
Started Aug 12 06:23:55 PM PDT 24
Finished Aug 12 06:23:57 PM PDT 24
Peak memory 222952 kb
Host smart-47fc2ae2-9e2f-4756-8883-c671f1655363
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726811164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.3726811164 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1770607290
Short name T829
Test name
Test status
Simulation time 1129123894 ps
CPU time 5.12 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 215084 kb
Host smart-0b1e8e95-f33d-4dd3-b787-371dc3a3dee3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770607290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1770
607290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2007267959
Short name T750
Test name
Test status
Simulation time 97453725 ps
CPU time 1.82 seconds
Started Aug 12 06:23:57 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 223276 kb
Host smart-ce41c95e-e196-4924-8dcb-79290c305e4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007267959 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2007267959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1129269823
Short name T815
Test name
Test status
Simulation time 20488712 ps
CPU time 1.02 seconds
Started Aug 12 06:23:45 PM PDT 24
Finished Aug 12 06:23:46 PM PDT 24
Peak memory 206816 kb
Host smart-a9fe2d7e-8b7b-475e-9a4f-488dca4d94fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129269823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1129269823 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.1934985394
Short name T737
Test name
Test status
Simulation time 22758952 ps
CPU time 0.73 seconds
Started Aug 12 06:23:44 PM PDT 24
Finished Aug 12 06:23:45 PM PDT 24
Peak memory 206612 kb
Host smart-3cdd876d-5cc5-4e62-8f85-ceccc5f38820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934985394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1934985394 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1286717706
Short name T823
Test name
Test status
Simulation time 62288163 ps
CPU time 1.52 seconds
Started Aug 12 06:23:54 PM PDT 24
Finished Aug 12 06:23:55 PM PDT 24
Peak memory 215252 kb
Host smart-0f56711b-6864-4d48-ae0b-024e3efe310c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286717706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.1286717706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.957300107
Short name T98
Test name
Test status
Simulation time 166113251 ps
CPU time 1.47 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 215636 kb
Host smart-08043719-356b-43b4-9d62-fad563fa5525
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957300107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_
errors.957300107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1941500724
Short name T769
Test name
Test status
Simulation time 65230979 ps
CPU time 1.73 seconds
Started Aug 12 06:23:46 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 215340 kb
Host smart-99216557-ec34-4ce5-b578-4b29ceff79fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941500724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.1941500724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1363636020
Short name T117
Test name
Test status
Simulation time 139676292 ps
CPU time 4.05 seconds
Started Aug 12 06:23:54 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 215212 kb
Host smart-efb87ce6-bb96-4572-9204-d1606578e776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363636020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1363636020 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3353174524
Short name T157
Test name
Test status
Simulation time 825591008 ps
CPU time 4.46 seconds
Started Aug 12 06:23:50 PM PDT 24
Finished Aug 12 06:23:54 PM PDT 24
Peak memory 206900 kb
Host smart-d32d14a2-3edb-4b13-9b2e-8d7476a52469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353174524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3353
174524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1060558117
Short name T828
Test name
Test status
Simulation time 200940110 ps
CPU time 2.7 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:24:01 PM PDT 24
Peak memory 223304 kb
Host smart-55425323-d702-4375-acb5-938ed13ab542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060558117 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1060558117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.772492688
Short name T814
Test name
Test status
Simulation time 79889659 ps
CPU time 1.13 seconds
Started Aug 12 06:23:41 PM PDT 24
Finished Aug 12 06:23:42 PM PDT 24
Peak memory 215064 kb
Host smart-09b0fae6-0df9-43f7-85cc-9a18b09e91bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772492688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.772492688 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.2972637739
Short name T799
Test name
Test status
Simulation time 20179364 ps
CPU time 0.82 seconds
Started Aug 12 06:23:37 PM PDT 24
Finished Aug 12 06:23:38 PM PDT 24
Peak memory 206564 kb
Host smart-6e6d480b-21d8-4b87-a07b-537a3f9490d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972637739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2972637739 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3448316495
Short name T813
Test name
Test status
Simulation time 229358723 ps
CPU time 1.54 seconds
Started Aug 12 06:23:59 PM PDT 24
Finished Aug 12 06:24:01 PM PDT 24
Peak memory 215648 kb
Host smart-931055fe-7559-4bc9-a03e-f45e328e9c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448316495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.3448316495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1017961169
Short name T794
Test name
Test status
Simulation time 108152726 ps
CPU time 1.02 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 215392 kb
Host smart-eae1ff02-3ce4-415c-adc8-692b45a948a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017961169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.1017961169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3050157377
Short name T826
Test name
Test status
Simulation time 36923282 ps
CPU time 1.36 seconds
Started Aug 12 06:23:45 PM PDT 24
Finished Aug 12 06:23:47 PM PDT 24
Peak memory 215152 kb
Host smart-1f175b58-c065-450e-b91e-a6250df14a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050157377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3050157377 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1973382825
Short name T158
Test name
Test status
Simulation time 809241112 ps
CPU time 2.81 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 215076 kb
Host smart-32320ffb-b728-4087-bb38-aaefa85c6af7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973382825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1973
382825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1860748881
Short name T867
Test name
Test status
Simulation time 477306987 ps
CPU time 2.35 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:07 PM PDT 24
Peak memory 216320 kb
Host smart-0569a5f3-5d04-4a87-8375-7e1e12d47ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860748881 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1860748881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.486803047
Short name T850
Test name
Test status
Simulation time 38541545 ps
CPU time 0.89 seconds
Started Aug 12 06:24:15 PM PDT 24
Finished Aug 12 06:24:16 PM PDT 24
Peak memory 206692 kb
Host smart-e8131077-f447-47f8-8d3e-d70e85128e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486803047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.486803047 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.3907879294
Short name T758
Test name
Test status
Simulation time 29339180 ps
CPU time 0.83 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:50 PM PDT 24
Peak memory 206644 kb
Host smart-cdedc205-5373-4cfc-9b47-0006c8bd1879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907879294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3907879294 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2446272015
Short name T844
Test name
Test status
Simulation time 37913235 ps
CPU time 2.13 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 215384 kb
Host smart-a0e046b3-7566-49c8-a718-6754b863d9bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446272015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.2446272015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.375277352
Short name T779
Test name
Test status
Simulation time 61856776 ps
CPU time 1.44 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 215540 kb
Host smart-12932373-c9ea-4dd1-bf9f-4a1a4db58ba7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375277352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.375277352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4236541641
Short name T738
Test name
Test status
Simulation time 573387932 ps
CPU time 1.79 seconds
Started Aug 12 06:23:37 PM PDT 24
Finished Aug 12 06:23:39 PM PDT 24
Peak memory 215620 kb
Host smart-22838ea2-fde1-4a67-b68c-c086dc321dd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236541641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.4236541641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.829408396
Short name T811
Test name
Test status
Simulation time 96864835 ps
CPU time 1.76 seconds
Started Aug 12 06:23:42 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 215280 kb
Host smart-0525ba8e-24e5-4bfa-93b3-17f253e0dbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829408396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.829408396 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2282271993
Short name T161
Test name
Test status
Simulation time 833724008 ps
CPU time 4.61 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:54 PM PDT 24
Peak memory 217944 kb
Host smart-9e543a4c-9fb0-49fb-bf33-2ee31ff550e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282271993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2282
271993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2320847804
Short name T786
Test name
Test status
Simulation time 75244162 ps
CPU time 2.42 seconds
Started Aug 12 06:23:48 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 216532 kb
Host smart-55f33808-bdc7-416e-8b63-15fd1c1ec94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320847804 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2320847804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3504686876
Short name T858
Test name
Test status
Simulation time 19079234 ps
CPU time 1.07 seconds
Started Aug 12 06:23:48 PM PDT 24
Finished Aug 12 06:23:49 PM PDT 24
Peak memory 206900 kb
Host smart-552d14e0-d15f-4ecb-82c6-d17a59964df7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504686876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3504686876 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.2591771031
Short name T729
Test name
Test status
Simulation time 25957309 ps
CPU time 0.77 seconds
Started Aug 12 06:23:55 PM PDT 24
Finished Aug 12 06:23:55 PM PDT 24
Peak memory 206584 kb
Host smart-edc12520-0e15-492d-9e81-f99a1c72c660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591771031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2591771031 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1898351838
Short name T751
Test name
Test status
Simulation time 253577703 ps
CPU time 1.65 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:58 PM PDT 24
Peak memory 215324 kb
Host smart-49cb6d4b-abb4-4739-a410-907f52df7bfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898351838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.1898351838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4013613704
Short name T94
Test name
Test status
Simulation time 70211365 ps
CPU time 1.2 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 215620 kb
Host smart-e5d767b3-c41e-49d5-8866-3ccf57da5eed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013613704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.4013613704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3191303299
Short name T847
Test name
Test status
Simulation time 129584745 ps
CPU time 2.74 seconds
Started Aug 12 06:23:50 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 223412 kb
Host smart-1e581fff-d85d-445f-bf48-e425ef227d11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191303299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.3191303299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2952164760
Short name T121
Test name
Test status
Simulation time 244147283 ps
CPU time 3.58 seconds
Started Aug 12 06:23:57 PM PDT 24
Finished Aug 12 06:24:00 PM PDT 24
Peak memory 215164 kb
Host smart-634a9751-3ade-4aa1-adaa-bb922378b3de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952164760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2952164760 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3211749467
Short name T802
Test name
Test status
Simulation time 789370845 ps
CPU time 2.79 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 206908 kb
Host smart-8c69b7ec-c134-49e6-9d58-ea36a683b6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211749467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3211
749467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1738875182
Short name T864
Test name
Test status
Simulation time 394700617 ps
CPU time 8.77 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:37 PM PDT 24
Peak memory 206880 kb
Host smart-f338679b-24aa-4bcd-a5f5-0ec57891510d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738875182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1738875
182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1229888515
Short name T812
Test name
Test status
Simulation time 1166917839 ps
CPU time 14.87 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 206912 kb
Host smart-a6a3723e-0ba0-4adb-b089-7812c64a9282
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229888515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1229888
515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3999609835
Short name T726
Test name
Test status
Simulation time 53164833 ps
CPU time 1.1 seconds
Started Aug 12 06:23:29 PM PDT 24
Finished Aug 12 06:23:30 PM PDT 24
Peak memory 215040 kb
Host smart-9769db7c-e38f-4d57-ad92-653692a72246
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999609835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3999609
835 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2013532460
Short name T125
Test name
Test status
Simulation time 41982928 ps
CPU time 1.51 seconds
Started Aug 12 06:23:30 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 215108 kb
Host smart-8ec812b4-f78f-4fae-b7ab-2691355035e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013532460 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2013532460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.521110455
Short name T837
Test name
Test status
Simulation time 25826132 ps
CPU time 1.11 seconds
Started Aug 12 06:23:21 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 206836 kb
Host smart-fd1dacce-5a6b-40a8-9139-e5b6105890c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521110455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.521110455 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.3442124562
Short name T791
Test name
Test status
Simulation time 16833206 ps
CPU time 0.79 seconds
Started Aug 12 06:23:26 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 206636 kb
Host smart-f3434ee2-98b8-45f5-8bd2-c59af29ee7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442124562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3442124562 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1297942212
Short name T862
Test name
Test status
Simulation time 11288969 ps
CPU time 0.71 seconds
Started Aug 12 06:23:24 PM PDT 24
Finished Aug 12 06:23:25 PM PDT 24
Peak memory 206628 kb
Host smart-3b2ab3f5-7857-4128-b722-52e1caa505bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297942212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1297942212
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.192647864
Short name T765
Test name
Test status
Simulation time 270649120 ps
CPU time 2.3 seconds
Started Aug 12 06:23:36 PM PDT 24
Finished Aug 12 06:23:38 PM PDT 24
Peak memory 215052 kb
Host smart-a79357cf-e8c4-4082-9b78-f2bd5687c03d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192647864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_
outstanding.192647864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1117857818
Short name T88
Test name
Test status
Simulation time 29055601 ps
CPU time 0.99 seconds
Started Aug 12 06:23:14 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 215384 kb
Host smart-fb744a1e-80d8-4fd7-ad7a-714ed26e0c2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117857818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.1117857818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.264896736
Short name T825
Test name
Test status
Simulation time 250929601 ps
CPU time 2.79 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:37 PM PDT 24
Peak memory 215560 kb
Host smart-2f6205d3-f369-49e3-acad-ee50540842cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264896736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_
shadow_reg_errors_with_csr_rw.264896736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.823169190
Short name T810
Test name
Test status
Simulation time 149349522 ps
CPU time 3.6 seconds
Started Aug 12 06:23:29 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 215120 kb
Host smart-6f5b05c7-9702-4c4b-98ff-45dd275c48f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823169190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.823169190 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1263834823
Short name T160
Test name
Test status
Simulation time 185424340 ps
CPU time 2.38 seconds
Started Aug 12 06:23:30 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 214988 kb
Host smart-ddaa8671-621a-4b68-b7c0-3d19f944e0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263834823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.12638
34823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.2447436213
Short name T782
Test name
Test status
Simulation time 37111765 ps
CPU time 0.72 seconds
Started Aug 12 06:23:50 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 206576 kb
Host smart-29664796-c173-46fd-bc77-d5677bc59c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447436213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2447436213 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.3626575466
Short name T148
Test name
Test status
Simulation time 23445693 ps
CPU time 0.78 seconds
Started Aug 12 06:23:51 PM PDT 24
Finished Aug 12 06:23:52 PM PDT 24
Peak memory 206604 kb
Host smart-72c7eab6-ea01-4a5b-98e2-d5f3a21ee2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626575466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3626575466 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.391484618
Short name T793
Test name
Test status
Simulation time 16730979 ps
CPU time 0.79 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 206592 kb
Host smart-17693ecb-1473-445f-a5b7-35987279dab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391484618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.391484618 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2946013490
Short name T114
Test name
Test status
Simulation time 14848646 ps
CPU time 0.77 seconds
Started Aug 12 06:24:10 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 206648 kb
Host smart-51f6029a-fdf1-4f20-a2a8-8a036b906733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946013490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2946013490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2727802155
Short name T150
Test name
Test status
Simulation time 31407869 ps
CPU time 0.79 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 206648 kb
Host smart-81be8139-6998-4c8d-9ab5-231a963c8a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727802155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2727802155 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2125162909
Short name T808
Test name
Test status
Simulation time 28165059 ps
CPU time 0.73 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:57 PM PDT 24
Peak memory 206532 kb
Host smart-1791eb44-b49e-4b4f-9f3d-92e1a32ef4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125162909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2125162909 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2731172196
Short name T861
Test name
Test status
Simulation time 18358599 ps
CPU time 0.8 seconds
Started Aug 12 06:23:46 PM PDT 24
Finished Aug 12 06:23:47 PM PDT 24
Peak memory 206664 kb
Host smart-2cf25df9-cd91-40bb-9596-5240856a7c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731172196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2731172196 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.3813891465
Short name T771
Test name
Test status
Simulation time 20728206 ps
CPU time 0.73 seconds
Started Aug 12 06:23:59 PM PDT 24
Finished Aug 12 06:24:00 PM PDT 24
Peak memory 206520 kb
Host smart-6044a023-a284-431d-ac4f-761efa5d56f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813891465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3813891465 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.4123210279
Short name T149
Test name
Test status
Simulation time 35601059 ps
CPU time 0.77 seconds
Started Aug 12 06:23:50 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 206604 kb
Host smart-bfddbdb4-fa3f-43e4-a66e-7d4c750b7fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123210279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.4123210279 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3844366803
Short name T868
Test name
Test status
Simulation time 12498043 ps
CPU time 0.72 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:57 PM PDT 24
Peak memory 206524 kb
Host smart-33da7d5c-2808-4c27-b690-55c3f0f99e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844366803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3844366803 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1092970507
Short name T820
Test name
Test status
Simulation time 380623765 ps
CPU time 5.08 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 207128 kb
Host smart-ddbd1016-e419-41a6-b9c4-7a56dfc942e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092970507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1092970
507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3302151731
Short name T801
Test name
Test status
Simulation time 1172355381 ps
CPU time 15.32 seconds
Started Aug 12 06:23:33 PM PDT 24
Finished Aug 12 06:23:48 PM PDT 24
Peak memory 206956 kb
Host smart-97aa3ea2-ce03-4742-9090-d4b3f2daffcc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302151731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3302151
731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3425507155
Short name T721
Test name
Test status
Simulation time 169685694 ps
CPU time 1.04 seconds
Started Aug 12 06:23:27 PM PDT 24
Finished Aug 12 06:23:28 PM PDT 24
Peak memory 206864 kb
Host smart-bb34bb24-6938-4322-af3b-422d4a867108
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425507155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3425507
155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3807975575
Short name T122
Test name
Test status
Simulation time 78380590 ps
CPU time 2.15 seconds
Started Aug 12 06:23:32 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 216200 kb
Host smart-eaaf383c-128b-4fe5-905a-5ec0965d2928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807975575 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3807975575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1269491042
Short name T870
Test name
Test status
Simulation time 58695543 ps
CPU time 0.9 seconds
Started Aug 12 06:23:26 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 206612 kb
Host smart-820257ae-e8aa-4d08-beb8-bf0735df0db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269491042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1269491042 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.2373088144
Short name T785
Test name
Test status
Simulation time 11125636 ps
CPU time 0.75 seconds
Started Aug 12 06:23:29 PM PDT 24
Finished Aug 12 06:23:30 PM PDT 24
Peak memory 206608 kb
Host smart-e92caf93-20af-4cf4-8a4a-106a337d5a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373088144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2373088144 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3034451139
Short name T130
Test name
Test status
Simulation time 111365683 ps
CPU time 1.2 seconds
Started Aug 12 06:23:37 PM PDT 24
Finished Aug 12 06:23:39 PM PDT 24
Peak memory 214924 kb
Host smart-d181e492-eec1-44de-948a-ef81968f8c1f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034451139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.3034451139 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1467286712
Short name T725
Test name
Test status
Simulation time 13055108 ps
CPU time 0.74 seconds
Started Aug 12 06:23:23 PM PDT 24
Finished Aug 12 06:23:29 PM PDT 24
Peak memory 206632 kb
Host smart-255b1c3a-bd42-45b6-92a4-de2a85f0c442
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467286712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1467286712
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2903285284
Short name T832
Test name
Test status
Simulation time 39552574 ps
CPU time 2 seconds
Started Aug 12 06:23:27 PM PDT 24
Finished Aug 12 06:23:29 PM PDT 24
Peak memory 215088 kb
Host smart-f9bf3144-6939-4d39-a886-6093eed2d904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903285284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.2903285284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2117490961
Short name T105
Test name
Test status
Simulation time 73239375 ps
CPU time 0.98 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 215460 kb
Host smart-ad5eed5f-1457-44cd-b5a9-88191c6f3d35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117490961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.2117490961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.331722467
Short name T843
Test name
Test status
Simulation time 420142824 ps
CPU time 3.02 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:25 PM PDT 24
Peak memory 215660 kb
Host smart-3e2ed8e2-ce2d-4b0f-a543-11bbae6f7a0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331722467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_
shadow_reg_errors_with_csr_rw.331722467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2972502605
Short name T50
Test name
Test status
Simulation time 27311089 ps
CPU time 1.66 seconds
Started Aug 12 06:23:32 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 215188 kb
Host smart-84994576-2f8c-46b5-acbb-bb3858a23380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972502605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2972502605 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2488518928
Short name T731
Test name
Test status
Simulation time 22853993 ps
CPU time 0.73 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 206648 kb
Host smart-ad6b7af9-5805-42d3-bd85-b22fafaf6374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488518928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2488518928 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.4028979052
Short name T866
Test name
Test status
Simulation time 11103726 ps
CPU time 0.73 seconds
Started Aug 12 06:23:45 PM PDT 24
Finished Aug 12 06:23:46 PM PDT 24
Peak memory 206612 kb
Host smart-bbc3a29d-7665-4ebf-a59a-4776cd5d5038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028979052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.4028979052 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.2975704100
Short name T787
Test name
Test status
Simulation time 22746746 ps
CPU time 0.76 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 206636 kb
Host smart-5265b6a1-0bde-4647-9e11-46cc4369ca9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975704100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2975704100 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.4176963162
Short name T822
Test name
Test status
Simulation time 72886420 ps
CPU time 0.73 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:57 PM PDT 24
Peak memory 206520 kb
Host smart-49c4b885-1389-4d2e-a308-e28f1b1cb97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176963162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.4176963162 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.4211586854
Short name T851
Test name
Test status
Simulation time 38926899 ps
CPU time 0.72 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 206628 kb
Host smart-c2c08bfd-47e1-4204-bea1-ffef84273cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211586854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.4211586854 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3602977787
Short name T780
Test name
Test status
Simulation time 32715803 ps
CPU time 0.8 seconds
Started Aug 12 06:23:55 PM PDT 24
Finished Aug 12 06:23:56 PM PDT 24
Peak memory 206552 kb
Host smart-76d7cc96-6772-4c16-aaa1-ceefc8dbb473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602977787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3602977787 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.1850948017
Short name T833
Test name
Test status
Simulation time 31142931 ps
CPU time 0.77 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 206612 kb
Host smart-14756784-55a0-4caf-adb0-b3ed4119e109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850948017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1850948017 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.3373327776
Short name T762
Test name
Test status
Simulation time 35139122 ps
CPU time 0.74 seconds
Started Aug 12 06:23:50 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 206588 kb
Host smart-928a9f7b-7e1e-4801-9459-3986c5ebef73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373327776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3373327776 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1813599159
Short name T781
Test name
Test status
Simulation time 24699813 ps
CPU time 0.74 seconds
Started Aug 12 06:23:55 PM PDT 24
Finished Aug 12 06:23:56 PM PDT 24
Peak memory 206636 kb
Host smart-8f37aa64-4324-4501-a828-650c9951a8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813599159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1813599159 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.2859342465
Short name T783
Test name
Test status
Simulation time 20555422 ps
CPU time 0.77 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 206620 kb
Host smart-7985d201-fc14-4933-86b3-1e109783ac52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859342465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2859342465 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1465774241
Short name T819
Test name
Test status
Simulation time 222073802 ps
CPU time 4.9 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 206840 kb
Host smart-cb44374a-25e3-4e3f-85cc-f82bcb33ddfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465774241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1465774
241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3138783126
Short name T831
Test name
Test status
Simulation time 4612763967 ps
CPU time 20.26 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:24:03 PM PDT 24
Peak memory 206908 kb
Host smart-0d03269b-1802-4232-a688-4926df3c98bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138783126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3138783
126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.532410583
Short name T767
Test name
Test status
Simulation time 37772168 ps
CPU time 1.12 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 206908 kb
Host smart-8317ecc5-03f4-43c4-8cbb-82208cfc9aed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532410583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.53241058
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2779923222
Short name T807
Test name
Test status
Simulation time 272958962 ps
CPU time 2.12 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:24 PM PDT 24
Peak memory 223364 kb
Host smart-8c86d376-8bbb-4446-974f-975abce91d02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779923222 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2779923222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1507668141
Short name T162
Test name
Test status
Simulation time 54468307 ps
CPU time 1.15 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:57 PM PDT 24
Peak memory 206900 kb
Host smart-60021602-8b70-4d6c-9727-4f7442a6505b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507668141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1507668141 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3430274710
Short name T778
Test name
Test status
Simulation time 29042783 ps
CPU time 0.78 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:53 PM PDT 24
Peak memory 206616 kb
Host smart-3c711f11-2648-471b-a21a-8344d8539ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430274710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3430274710 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.412767811
Short name T131
Test name
Test status
Simulation time 32959992 ps
CPU time 1.27 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 215068 kb
Host smart-0c2155f0-279b-42ce-83d2-0506933025cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412767811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial
_access.412767811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1351499908
Short name T720
Test name
Test status
Simulation time 32502374 ps
CPU time 0.68 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 206580 kb
Host smart-e842ce11-edb3-4eb3-a3d8-12916ce4f3c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351499908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1351499908
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3371342482
Short name T723
Test name
Test status
Simulation time 47384668 ps
CPU time 1.47 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 215336 kb
Host smart-50611500-9da3-45b8-8da5-ce8fe460fec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371342482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3371342482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1703317300
Short name T834
Test name
Test status
Simulation time 120471873 ps
CPU time 1.2 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 215768 kb
Host smart-da090efe-ce79-4dd9-9e51-5f92b1fb9ae8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703317300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.1703317300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.401268242
Short name T839
Test name
Test status
Simulation time 62970743 ps
CPU time 1.53 seconds
Started Aug 12 06:23:30 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 215276 kb
Host smart-1bb1321d-f0c4-4f8b-a4f3-0572a2f37651
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401268242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_
shadow_reg_errors_with_csr_rw.401268242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.301544404
Short name T120
Test name
Test status
Simulation time 31802388 ps
CPU time 1.99 seconds
Started Aug 12 06:23:24 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 218396 kb
Host smart-e7745571-4fcd-4296-a0c3-e3d83bed9eac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301544404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.301544404 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3256158429
Short name T770
Test name
Test status
Simulation time 480868139 ps
CPU time 2.81 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:25 PM PDT 24
Peak memory 206868 kb
Host smart-6c822e0c-4412-4e10-9292-8f90cee78ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256158429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.32561
58429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.71196711
Short name T112
Test name
Test status
Simulation time 22696957 ps
CPU time 0.74 seconds
Started Aug 12 06:23:57 PM PDT 24
Finished Aug 12 06:23:58 PM PDT 24
Peak memory 206624 kb
Host smart-e646af0f-88ef-4f91-b4e2-6b9856659d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71196711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.71196711 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2549858449
Short name T772
Test name
Test status
Simulation time 18632973 ps
CPU time 0.78 seconds
Started Aug 12 06:24:09 PM PDT 24
Finished Aug 12 06:24:10 PM PDT 24
Peak memory 206516 kb
Host smart-10dbaa99-5398-4370-8203-dd12833bf3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549858449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2549858449 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.873407279
Short name T759
Test name
Test status
Simulation time 18084115 ps
CPU time 0.81 seconds
Started Aug 12 06:24:01 PM PDT 24
Finished Aug 12 06:24:02 PM PDT 24
Peak memory 206620 kb
Host smart-4a5dd9f3-4bf7-4048-aefe-b27cfc6c26e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873407279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.873407279 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.3335768194
Short name T752
Test name
Test status
Simulation time 89665157 ps
CPU time 0.76 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:23:57 PM PDT 24
Peak memory 206628 kb
Host smart-6ccc5a82-bee4-4c04-896d-9bc64101ac28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335768194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3335768194 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3505756512
Short name T869
Test name
Test status
Simulation time 39010991 ps
CPU time 0.81 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 206648 kb
Host smart-7df38619-9fac-42fc-bfbe-fee9a7cd6b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505756512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3505756512 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.1453342108
Short name T776
Test name
Test status
Simulation time 17605295 ps
CPU time 0.78 seconds
Started Aug 12 06:24:00 PM PDT 24
Finished Aug 12 06:24:01 PM PDT 24
Peak memory 206604 kb
Host smart-d2a8e023-0f49-438d-861f-3b941673a167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453342108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1453342108 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1424908859
Short name T798
Test name
Test status
Simulation time 22386241 ps
CPU time 0.74 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 206604 kb
Host smart-a4f5a976-b278-4e40-805e-e49f17577ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424908859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1424908859 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1401744416
Short name T784
Test name
Test status
Simulation time 31473609 ps
CPU time 0.79 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 206608 kb
Host smart-f073eb45-8f99-432b-8727-10e236634bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401744416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1401744416 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.264012931
Short name T805
Test name
Test status
Simulation time 669240283 ps
CPU time 2.51 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:52 PM PDT 24
Peak memory 216432 kb
Host smart-aef4d7f8-b507-4607-bfd8-a8214f22d6ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264012931 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.264012931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2653960803
Short name T136
Test name
Test status
Simulation time 206799001 ps
CPU time 1.17 seconds
Started Aug 12 06:23:46 PM PDT 24
Finished Aug 12 06:23:47 PM PDT 24
Peak memory 206828 kb
Host smart-fdef5c69-22fb-4976-9f10-461a75d952d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653960803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2653960803 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1178072193
Short name T761
Test name
Test status
Simulation time 156600281 ps
CPU time 0.72 seconds
Started Aug 12 06:23:26 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 206592 kb
Host smart-a58d01e7-fbb3-42e7-87b6-d71bc9cc2360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178072193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1178072193 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1171883838
Short name T824
Test name
Test status
Simulation time 25651053 ps
CPU time 1.53 seconds
Started Aug 12 06:23:42 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 215148 kb
Host smart-d733696c-d75e-4dc8-ac88-47d2dace15b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171883838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.1171883838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.329009256
Short name T740
Test name
Test status
Simulation time 40915183 ps
CPU time 1.16 seconds
Started Aug 12 06:23:33 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 215632 kb
Host smart-70b61169-1bad-42e8-98ec-b05076c469c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329009256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.329009256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2562719205
Short name T790
Test name
Test status
Simulation time 235325009 ps
CPU time 1.86 seconds
Started Aug 12 06:23:38 PM PDT 24
Finished Aug 12 06:23:40 PM PDT 24
Peak memory 215640 kb
Host smart-cb5665a6-ec5c-4dbf-965f-b2d2783373d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562719205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.2562719205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3759542643
Short name T110
Test name
Test status
Simulation time 124563082 ps
CPU time 1.55 seconds
Started Aug 12 06:23:38 PM PDT 24
Finished Aug 12 06:23:45 PM PDT 24
Peak memory 215136 kb
Host smart-30bb0450-99c2-43b7-807e-d0c41f763ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759542643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3759542643 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.25905092
Short name T123
Test name
Test status
Simulation time 264808045 ps
CPU time 2.41 seconds
Started Aug 12 06:23:37 PM PDT 24
Finished Aug 12 06:23:40 PM PDT 24
Peak memory 215120 kb
Host smart-f089bb65-842c-4bf1-9429-0e830b089049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25905092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.2590509
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.925298410
Short name T852
Test name
Test status
Simulation time 27868698 ps
CPU time 1.47 seconds
Started Aug 12 06:23:32 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 215512 kb
Host smart-a8b2610d-b9b9-40eb-b39c-bf51d0a6f9e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925298410 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.925298410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3489156927
Short name T727
Test name
Test status
Simulation time 33618772 ps
CPU time 1.22 seconds
Started Aug 12 06:23:48 PM PDT 24
Finished Aug 12 06:23:50 PM PDT 24
Peak memory 215036 kb
Host smart-0a75ebd4-2a48-4386-a197-e5a2a71f9c71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489156927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3489156927 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.3193507850
Short name T146
Test name
Test status
Simulation time 17021594 ps
CPU time 0.75 seconds
Started Aug 12 06:23:42 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 206512 kb
Host smart-6a842624-8cc7-4270-9a36-ce8a4743b5fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193507850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3193507850 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2802259465
Short name T777
Test name
Test status
Simulation time 362208631 ps
CPU time 2.42 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:42 PM PDT 24
Peak memory 215120 kb
Host smart-d77c30fe-43d9-4d88-ac33-a5cdc3c37390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802259465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.2802259465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1537723633
Short name T853
Test name
Test status
Simulation time 123903410 ps
CPU time 1.2 seconds
Started Aug 12 06:23:37 PM PDT 24
Finished Aug 12 06:23:39 PM PDT 24
Peak memory 215644 kb
Host smart-ffff8a08-87a5-4991-8fb7-eae1bbdfd1ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537723633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1537723633 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1029082909
Short name T96
Test name
Test status
Simulation time 204990498 ps
CPU time 2.41 seconds
Started Aug 12 06:23:40 PM PDT 24
Finished Aug 12 06:23:42 PM PDT 24
Peak memory 215640 kb
Host smart-8a72fcf6-b7e0-473c-bb17-6d6bd6196454
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029082909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1029082909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3095543158
Short name T118
Test name
Test status
Simulation time 229856480 ps
CPU time 2.27 seconds
Started Aug 12 06:23:20 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 215172 kb
Host smart-dd718863-a28c-4ac9-9342-ad32b8ed5e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095543158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3095543158 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1484786021
Short name T104
Test name
Test status
Simulation time 1198637515 ps
CPU time 4.04 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:51 PM PDT 24
Peak memory 206924 kb
Host smart-e4bcdd5b-ed23-45bb-92dd-8eb4e091ab99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484786021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.14847
86021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3396948754
Short name T748
Test name
Test status
Simulation time 42038409 ps
CPU time 1.49 seconds
Started Aug 12 06:23:41 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 215072 kb
Host smart-7359c464-040a-4340-b09f-a98ceb07fb2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396948754 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3396948754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.601622759
Short name T732
Test name
Test status
Simulation time 13093420 ps
CPU time 0.9 seconds
Started Aug 12 06:23:29 PM PDT 24
Finished Aug 12 06:23:30 PM PDT 24
Peak memory 206596 kb
Host smart-0db0f561-12db-46da-9fc1-193ac23ca5f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601622759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.601622759 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3242112635
Short name T735
Test name
Test status
Simulation time 32323131 ps
CPU time 0.73 seconds
Started Aug 12 06:23:43 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 206680 kb
Host smart-06671ec9-8d36-49d0-89a4-c9f985fc65ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242112635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3242112635 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.810182502
Short name T736
Test name
Test status
Simulation time 72736276 ps
CPU time 2.08 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 215356 kb
Host smart-e3640267-9698-4a0a-bcaa-37c422607eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810182502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_
outstanding.810182502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1655342261
Short name T792
Test name
Test status
Simulation time 56481770 ps
CPU time 1.7 seconds
Started Aug 12 06:23:32 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 215676 kb
Host smart-5528cfe7-1e53-4428-8905-fed5a5fa8143
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655342261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1655342261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.3515745354
Short name T795
Test name
Test status
Simulation time 129132745 ps
CPU time 2.58 seconds
Started Aug 12 06:23:26 PM PDT 24
Finished Aug 12 06:23:29 PM PDT 24
Peak memory 223336 kb
Host smart-40e27b93-dfd7-4eb0-b185-aa9c6a22d9da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515745354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3515745354 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3552549632
Short name T106
Test name
Test status
Simulation time 263758556 ps
CPU time 2.91 seconds
Started Aug 12 06:23:38 PM PDT 24
Finished Aug 12 06:23:41 PM PDT 24
Peak memory 215160 kb
Host smart-762f9034-f13f-44f2-ace6-5483997f52c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552549632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.35525
49632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3287362276
Short name T863
Test name
Test status
Simulation time 140478030 ps
CPU time 2.21 seconds
Started Aug 12 06:23:38 PM PDT 24
Finished Aug 12 06:23:41 PM PDT 24
Peak memory 216500 kb
Host smart-87ae424c-2329-47fd-8558-6593cb19ed5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287362276 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3287362276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1774014343
Short name T722
Test name
Test status
Simulation time 36519292 ps
CPU time 0.91 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:23:50 PM PDT 24
Peak memory 206672 kb
Host smart-b7bea27b-aeda-436a-9cd8-7e6749579af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774014343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1774014343 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.2290386425
Short name T139
Test name
Test status
Simulation time 120795124 ps
CPU time 0.76 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 206612 kb
Host smart-ff4bae6b-61a3-46ef-825e-22ac2227cd94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290386425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2290386425 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1375218356
Short name T137
Test name
Test status
Simulation time 102199643 ps
CPU time 2.3 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:49 PM PDT 24
Peak memory 215088 kb
Host smart-36d5dbee-5c74-43b9-a8f1-6dde37d42c0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375218356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.1375218356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2085552912
Short name T749
Test name
Test status
Simulation time 64744985 ps
CPU time 1.03 seconds
Started Aug 12 06:23:36 PM PDT 24
Finished Aug 12 06:23:37 PM PDT 24
Peak memory 215588 kb
Host smart-ba5ee326-a0f5-495b-86af-a17c36b9729d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085552912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2085552912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1314277423
Short name T91
Test name
Test status
Simulation time 619540613 ps
CPU time 2.69 seconds
Started Aug 12 06:23:24 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 223612 kb
Host smart-1b0de3bb-9091-44e8-80e2-3bf301108722
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314277423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.1314277423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2941793170
Short name T124
Test name
Test status
Simulation time 356370402 ps
CPU time 3.92 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:38 PM PDT 24
Peak memory 215144 kb
Host smart-8bb9e55e-5622-43bd-9927-a22c3ae9df65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941793170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.29417
93170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3814708031
Short name T835
Test name
Test status
Simulation time 22083048 ps
CPU time 1.52 seconds
Started Aug 12 06:23:36 PM PDT 24
Finished Aug 12 06:23:37 PM PDT 24
Peak memory 223296 kb
Host smart-1b4466e0-832f-41e2-bfca-8e26142c27d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814708031 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3814708031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3608370009
Short name T855
Test name
Test status
Simulation time 49380908 ps
CPU time 1.14 seconds
Started Aug 12 06:23:41 PM PDT 24
Finished Aug 12 06:23:42 PM PDT 24
Peak memory 206888 kb
Host smart-2a243302-502b-4328-b487-de518a23718f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608370009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3608370009 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3350421993
Short name T763
Test name
Test status
Simulation time 42576211 ps
CPU time 0.76 seconds
Started Aug 12 06:23:33 PM PDT 24
Finished Aug 12 06:23:34 PM PDT 24
Peak memory 206644 kb
Host smart-cfca07cf-9356-400a-a5f3-4119781e80d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350421993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3350421993 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2866124085
Short name T789
Test name
Test status
Simulation time 338792100 ps
CPU time 2.24 seconds
Started Aug 12 06:23:40 PM PDT 24
Finished Aug 12 06:23:42 PM PDT 24
Peak memory 215624 kb
Host smart-e6313597-d6a5-4cd6-9fcc-be94a1d757de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866124085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2866124085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2146349992
Short name T93
Test name
Test status
Simulation time 104072675 ps
CPU time 1.41 seconds
Started Aug 12 06:23:44 PM PDT 24
Finished Aug 12 06:23:46 PM PDT 24
Peak memory 215668 kb
Host smart-e8bcf0d8-b3b6-418b-b1d1-b127092111e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146349992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.2146349992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1249170086
Short name T744
Test name
Test status
Simulation time 83305616 ps
CPU time 2.11 seconds
Started Aug 12 06:23:30 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 215556 kb
Host smart-107c8954-86b5-4d3e-b134-98a37c301a7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249170086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1249170086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.900940204
Short name T49
Test name
Test status
Simulation time 28985445 ps
CPU time 1.64 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:30 PM PDT 24
Peak memory 215124 kb
Host smart-bf01f975-c937-4869-9a1d-f81ffbe640b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900940204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.900940204 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1067762211
Short name T153
Test name
Test status
Simulation time 261779302 ps
CPU time 5.02 seconds
Started Aug 12 06:23:32 PM PDT 24
Finished Aug 12 06:23:37 PM PDT 24
Peak memory 215080 kb
Host smart-7dd05bd5-802f-4be3-aea0-bb57eafd1ff2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067762211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.10677
62211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.2268402468
Short name T396
Test name
Test status
Simulation time 118074591 ps
CPU time 0.78 seconds
Started Aug 12 06:26:22 PM PDT 24
Finished Aug 12 06:26:23 PM PDT 24
Peak memory 205096 kb
Host smart-dc47d1b4-114d-4e41-8b19-8c81feb4aff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268402468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2268402468 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.1623335642
Short name T421
Test name
Test status
Simulation time 15958215492 ps
CPU time 202.27 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:29:38 PM PDT 24
Peak memory 298464 kb
Host smart-6c544046-43e0-4f70-938d-0d23399c1e9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623335642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1623335642 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.3299827402
Short name T259
Test name
Test status
Simulation time 2905891334 ps
CPU time 97.18 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:27:52 PM PDT 24
Peak memory 255220 kb
Host smart-14ba2551-23b4-4e3c-80f6-7749ce83591d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299827402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_par
tial_data.3299827402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2971272064
Short name T195
Test name
Test status
Simulation time 19482637813 ps
CPU time 763.84 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 06:38:52 PM PDT 24
Peak memory 252460 kb
Host smart-d2549ab0-48e3-46c7-ad13-03a00d8a937f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971272064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2971272064
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.3427152356
Short name T200
Test name
Test status
Simulation time 930123820 ps
CPU time 18.68 seconds
Started Aug 12 06:26:21 PM PDT 24
Finished Aug 12 06:26:39 PM PDT 24
Peak memory 223684 kb
Host smart-544dce71-7fcf-4318-b9b1-38d3e03e4e92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3427152356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3427152356 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.1315721435
Short name T608
Test name
Test status
Simulation time 4281357374 ps
CPU time 24.83 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:39 PM PDT 24
Peak memory 223696 kb
Host smart-a6d6b866-cd29-4f10-8685-f31d76ecad15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1315721435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1315721435 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.752718125
Short name T44
Test name
Test status
Simulation time 49292352530 ps
CPU time 71.46 seconds
Started Aug 12 06:26:20 PM PDT 24
Finished Aug 12 06:27:32 PM PDT 24
Peak memory 218836 kb
Host smart-e9ba269a-34b8-4612-bf71-d3f840a434ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752718125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.752718125 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.320097495
Short name T488
Test name
Test status
Simulation time 209831963239 ps
CPU time 239.18 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:30:14 PM PDT 24
Peak memory 425492 kb
Host smart-248c6ede-1ff0-48fb-b444-85f02bbecaa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320097495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.320
097495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.728448260
Short name T692
Test name
Test status
Simulation time 524427678 ps
CPU time 38.65 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:47 PM PDT 24
Peak memory 248520 kb
Host smart-5e677690-91a3-4171-8a0a-67dffb6c67f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728448260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.728448260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.158758912
Short name T599
Test name
Test status
Simulation time 3259932385 ps
CPU time 8.43 seconds
Started Aug 12 06:26:17 PM PDT 24
Finished Aug 12 06:26:25 PM PDT 24
Peak memory 217944 kb
Host smart-05036271-9974-4862-b81b-366b17fbd9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158758912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.158758912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.1595107187
Short name T53
Test name
Test status
Simulation time 101471780 ps
CPU time 1.18 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 218180 kb
Host smart-4f7d4ab6-424e-47d8-af72-7b19a957b447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595107187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1595107187 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3081726376
Short name T262
Test name
Test status
Simulation time 289000553641 ps
CPU time 591.29 seconds
Started Aug 12 06:26:20 PM PDT 24
Finished Aug 12 06:36:12 PM PDT 24
Peak memory 917992 kb
Host smart-49807841-c71a-4439-bafe-30fe9a1e88f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081726376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3081726376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.894959908
Short name T661
Test name
Test status
Simulation time 26943864623 ps
CPU time 73.61 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 284112 kb
Host smart-90d5db3f-35ef-4735-834d-9b5d1f24701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894959908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.894959908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1018415043
Short name T63
Test name
Test status
Simulation time 6299841954 ps
CPU time 29.39 seconds
Started Aug 12 06:26:24 PM PDT 24
Finished Aug 12 06:26:53 PM PDT 24
Peak memory 247116 kb
Host smart-d7185d19-afba-4098-92e1-5ee09342f006
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018415043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1018415043 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.391226587
Short name T566
Test name
Test status
Simulation time 24510734197 ps
CPU time 285.39 seconds
Started Aug 12 06:26:17 PM PDT 24
Finished Aug 12 06:31:02 PM PDT 24
Peak memory 346808 kb
Host smart-e62cc75a-2786-4c86-a66a-4a1eeef63acd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391226587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.391226587 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2613385373
Short name T410
Test name
Test status
Simulation time 909169431 ps
CPU time 49.26 seconds
Started Aug 12 06:26:36 PM PDT 24
Finished Aug 12 06:27:26 PM PDT 24
Peak memory 217756 kb
Host smart-fffba25b-6eb6-429b-9ba3-584b106e9127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613385373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2613385373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.3554430411
Short name T590
Test name
Test status
Simulation time 17236380660 ps
CPU time 131.61 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:28:26 PM PDT 24
Peak memory 261652 kb
Host smart-46d08e85-0526-40f7-84e5-98a73848568f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3554430411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3554430411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.780313067
Short name T69
Test name
Test status
Simulation time 172973457 ps
CPU time 2.2 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:16 PM PDT 24
Peak memory 217732 kb
Host smart-451d40fa-7a66-4326-b373-a91b87d7d254
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780313067 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_test_vectors_kmac.780313067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1529876054
Short name T403
Test name
Test status
Simulation time 111812443 ps
CPU time 2.15 seconds
Started Aug 12 06:26:21 PM PDT 24
Finished Aug 12 06:26:23 PM PDT 24
Peak memory 217776 kb
Host smart-37f06807-eff3-4fd5-abbc-3075f69b4128
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529876054 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1529876054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.1395417161
Short name T165
Test name
Test status
Simulation time 19606452558 ps
CPU time 50.15 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:27:04 PM PDT 24
Peak memory 246608 kb
Host smart-6381a15a-3b69-4670-b706-68f1d028735b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1395417161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1395417161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.696877095
Short name T439
Test name
Test status
Simulation time 252696179614 ps
CPU time 2805.51 seconds
Started Aug 12 06:26:10 PM PDT 24
Finished Aug 12 07:12:56 PM PDT 24
Peak memory 2995140 kb
Host smart-cf8b9b92-47d8-4061-83ff-d6d6360a910e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=696877095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.696877095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.3442739577
Short name T290
Test name
Test status
Simulation time 132224477860 ps
CPU time 1965.06 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:58:59 PM PDT 24
Peak memory 2277460 kb
Host smart-85a6618b-73da-4f41-a62e-ff3c9977ff88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3442739577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3442739577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.3537009381
Short name T219
Test name
Test status
Simulation time 5189616200 ps
CPU time 18.94 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 218088 kb
Host smart-377cf205-a141-4ebc-a3a6-4f224f1e65d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3537009381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3537009381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.604778868
Short name T347
Test name
Test status
Simulation time 20791474847 ps
CPU time 2172.94 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 07:02:22 PM PDT 24
Peak memory 1307832 kb
Host smart-98ea4cfe-c42f-4d3d-bc46-fef0e25a12b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=604778868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.604778868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.2548045282
Short name T307
Test name
Test status
Simulation time 1603669402 ps
CPU time 104.78 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:28:00 PM PDT 24
Peak memory 252916 kb
Host smart-450c3ba1-adb7-4f68-a51e-8339637f0271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2548045282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2548045282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.1542631660
Short name T289
Test name
Test status
Simulation time 24786484 ps
CPU time 0.76 seconds
Started Aug 12 06:26:24 PM PDT 24
Finished Aug 12 06:26:25 PM PDT 24
Peak memory 205080 kb
Host smart-52c4e446-df92-4268-8b3f-8e3a841d4c3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542631660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1542631660 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.3612478104
Short name T418
Test name
Test status
Simulation time 9497005924 ps
CPU time 73.48 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:27:29 PM PDT 24
Peak memory 276672 kb
Host smart-49cf827f-8471-4c6e-ae7c-46ade593d910
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612478104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3612478104 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.573212741
Short name T100
Test name
Test status
Simulation time 18002141282 ps
CPU time 77.26 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:27:30 PM PDT 24
Peak memory 282952 kb
Host smart-fbce6039-7847-4ab8-9954-7f60b2f4340b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573212741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_part
ial_data.573212741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.2567951696
Short name T40
Test name
Test status
Simulation time 30511517714 ps
CPU time 716.99 seconds
Started Aug 12 06:26:21 PM PDT 24
Finished Aug 12 06:38:18 PM PDT 24
Peak memory 239336 kb
Host smart-8d8b8426-8010-4cc8-8018-5cf99c767805
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567951696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2567951696
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.437996184
Short name T182
Test name
Test status
Simulation time 3414551857 ps
CPU time 7.15 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 223636 kb
Host smart-5ac592e7-8f5c-4da4-a167-4edc063534ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=437996184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.437996184 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2853872806
Short name T407
Test name
Test status
Simulation time 873953572 ps
CPU time 5.16 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 223628 kb
Host smart-b598213b-7690-4da1-a49e-27528293b370
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2853872806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2853872806 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.3251157081
Short name T214
Test name
Test status
Simulation time 3969897902 ps
CPU time 49.4 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:27:06 PM PDT 24
Peak memory 219012 kb
Host smart-d331940c-72cd-4997-b3cd-95129433e472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251157081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3251157081 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1764671297
Short name T288
Test name
Test status
Simulation time 23661182702 ps
CPU time 300.77 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:31:14 PM PDT 24
Peak memory 487808 kb
Host smart-a63c6e50-4d1b-4036-8944-368816806fc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764671297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.17
64671297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1935243923
Short name T436
Test name
Test status
Simulation time 8492041453 ps
CPU time 102.59 seconds
Started Aug 12 06:26:12 PM PDT 24
Finished Aug 12 06:27:55 PM PDT 24
Peak memory 273116 kb
Host smart-7715bb88-f115-428b-a855-14d6d2687026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935243923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1935243923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.768409745
Short name T260
Test name
Test status
Simulation time 2340917982 ps
CPU time 6.58 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:26:21 PM PDT 24
Peak memory 217708 kb
Host smart-cb93873a-9f08-4a85-a9eb-a3a9201fc741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768409745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.768409745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.3554706202
Short name T649
Test name
Test status
Simulation time 40176734 ps
CPU time 1.21 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:16 PM PDT 24
Peak memory 219112 kb
Host smart-002ca824-4780-41f1-b762-07f878b8f213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554706202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3554706202 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_mubi.2239511246
Short name T412
Test name
Test status
Simulation time 3676843630 ps
CPU time 203.28 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:29:33 PM PDT 24
Peak memory 306808 kb
Host smart-65a0b293-c15a-4c41-87cb-51cd632eb6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239511246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2239511246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.2156174336
Short name T620
Test name
Test status
Simulation time 10301428875 ps
CPU time 223.83 seconds
Started Aug 12 06:26:30 PM PDT 24
Finished Aug 12 06:30:14 PM PDT 24
Peak memory 320120 kb
Host smart-c0d7d7df-6bc4-4544-94d2-06d613ffcbb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156174336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2156174336 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2810218341
Short name T465
Test name
Test status
Simulation time 513332658 ps
CPU time 9.73 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:24 PM PDT 24
Peak memory 218752 kb
Host smart-7f4538b0-07e4-446e-874c-70a8c4d741e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810218341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2810218341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1774610764
Short name T546
Test name
Test status
Simulation time 30679790947 ps
CPU time 496.7 seconds
Started Aug 12 06:26:17 PM PDT 24
Finished Aug 12 06:34:34 PM PDT 24
Peak memory 696100 kb
Host smart-e2587b81-a88d-43f8-b1f9-b2feac2a1233
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1774610764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1774610764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.686004212
Short name T625
Test name
Test status
Simulation time 786907590 ps
CPU time 2.07 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:26:18 PM PDT 24
Peak memory 217588 kb
Host smart-fef3e51a-d6b1-4bd9-a83c-ec68217c5abd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686004212 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_test_vectors_kmac.686004212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3849570967
Short name T708
Test name
Test status
Simulation time 652950216 ps
CPU time 2.84 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:17 PM PDT 24
Peak memory 218084 kb
Host smart-b71634e5-3ac9-495a-b267-af0afb1a0969
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849570967 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3849570967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.2889292353
Short name T346
Test name
Test status
Simulation time 478061878842 ps
CPU time 3209.99 seconds
Started Aug 12 06:26:18 PM PDT 24
Finished Aug 12 07:19:49 PM PDT 24
Peak memory 3185576 kb
Host smart-b229832c-e397-4772-a7c2-003b38fdb112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2889292353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2889292353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.394304892
Short name T238
Test name
Test status
Simulation time 565275497 ps
CPU time 33.39 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:47 PM PDT 24
Peak memory 218444 kb
Host smart-37f61122-7b14-45d2-b8bb-092aeed66d6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=394304892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.394304892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.2963694279
Short name T330
Test name
Test status
Simulation time 60887841569 ps
CPU time 1199.22 seconds
Started Aug 12 06:26:17 PM PDT 24
Finished Aug 12 06:46:16 PM PDT 24
Peak memory 903652 kb
Host smart-dd0634f9-ee02-4020-b7fb-854636a625b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2963694279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2963694279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.1881463574
Short name T2
Test name
Test status
Simulation time 48637983497 ps
CPU time 1487 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:51:02 PM PDT 24
Peak memory 1731348 kb
Host smart-1f8613b6-3e38-401d-bdd9-e15bf217ea8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1881463574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1881463574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.652471940
Short name T204
Test name
Test status
Simulation time 3709155337 ps
CPU time 177.34 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:29:12 PM PDT 24
Peak memory 230168 kb
Host smart-97584a23-e9b1-4489-a3ee-c33f1e88f2ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=652471940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.652471940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.250349910
Short name T614
Test name
Test status
Simulation time 16148392382 ps
CPU time 367.61 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:32:22 PM PDT 24
Peak memory 350620 kb
Host smart-a7b21c53-9d44-4be3-961d-336f2b8c1ffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=250349910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.250349910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.1149690112
Short name T368
Test name
Test status
Simulation time 20477648 ps
CPU time 0.83 seconds
Started Aug 12 06:26:53 PM PDT 24
Finished Aug 12 06:26:54 PM PDT 24
Peak memory 204996 kb
Host smart-8cc750b9-753f-48c7-9ad0-fc357a7b4f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149690112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1149690112 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.1860401953
Short name T184
Test name
Test status
Simulation time 3547640507 ps
CPU time 43.24 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:27:26 PM PDT 24
Peak memory 253880 kb
Host smart-f7178334-9cab-4823-a5e5-635810de6451
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860401953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1860401953 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.2047331086
Short name T39
Test name
Test status
Simulation time 649602748 ps
CPU time 61.92 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:27:42 PM PDT 24
Peak memory 218464 kb
Host smart-8dba8d6a-539f-41f4-a9e9-6f846c8a3c61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047331086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.204733108
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2975628820
Short name T176
Test name
Test status
Simulation time 429528273 ps
CPU time 10.11 seconds
Started Aug 12 06:26:51 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 215512 kb
Host smart-d4bdbc82-3cfd-4d97-aa75-900b7474267d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2975628820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2975628820 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.192579237
Short name T202
Test name
Test status
Simulation time 554622361 ps
CPU time 19.24 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:27:03 PM PDT 24
Peak memory 223684 kb
Host smart-b31b2ffa-284c-4608-9cf3-426a2e83f919
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=192579237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.192579237 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.3742937201
Short name T647
Test name
Test status
Simulation time 36015328525 ps
CPU time 279.54 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 06:31:26 PM PDT 24
Peak memory 460520 kb
Host smart-0b7b5629-81ec-49c4-a0ca-44404ee551c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742937201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3
742937201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.2321001565
Short name T663
Test name
Test status
Simulation time 10992406335 ps
CPU time 78.35 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:28:01 PM PDT 24
Peak memory 293408 kb
Host smart-7e3dd89d-27ac-422d-92b3-fd87523721e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321001565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2321001565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.2077740066
Short name T283
Test name
Test status
Simulation time 2468317665 ps
CPU time 6.44 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:26:47 PM PDT 24
Peak memory 219016 kb
Host smart-f289e2d6-b977-4de1-9981-c758a6235fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077740066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2077740066 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.3419592168
Short name T329
Test name
Test status
Simulation time 51912199 ps
CPU time 1.55 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:26:47 PM PDT 24
Peak memory 217164 kb
Host smart-f55f06c7-8efb-47de-9c59-92ad134f1987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419592168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3419592168 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_sideload.355720425
Short name T82
Test name
Test status
Simulation time 1092386111 ps
CPU time 28.69 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:27:15 PM PDT 24
Peak memory 245396 kb
Host smart-656f78a1-f72c-450f-8574-e539b67aa4b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355720425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.355720425 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.3884045376
Short name T292
Test name
Test status
Simulation time 459335669 ps
CPU time 6.34 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:26:52 PM PDT 24
Peak memory 218484 kb
Host smart-e7b54ee2-3f8a-4066-90ee-424d5aa128cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884045376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3884045376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2861694928
Short name T480
Test name
Test status
Simulation time 11136307810 ps
CPU time 929.61 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:42:12 PM PDT 24
Peak memory 517780 kb
Host smart-80fa633e-6f61-472a-8847-58167b7a0fe7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2861694928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2861694928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_alert_test.3224059459
Short name T669
Test name
Test status
Simulation time 38076767 ps
CPU time 0.77 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:27:08 PM PDT 24
Peak memory 205036 kb
Host smart-885eb596-9bb1-48a3-9b54-8d00b83f5269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224059459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3224059459 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2704615090
Short name T393
Test name
Test status
Simulation time 3502624510 ps
CPU time 62.68 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:27:59 PM PDT 24
Peak memory 271884 kb
Host smart-f9a04910-0b01-42c5-9a61-800860eb0543
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704615090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2704615090 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3176841425
Short name T523
Test name
Test status
Simulation time 164626718792 ps
CPU time 1218.86 seconds
Started Aug 12 06:26:54 PM PDT 24
Finished Aug 12 06:47:13 PM PDT 24
Peak memory 263280 kb
Host smart-ebfc7d0b-0db8-4135-b94c-122447956ae2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176841425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.317684142
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.861125817
Short name T299
Test name
Test status
Simulation time 957061754 ps
CPU time 17.81 seconds
Started Aug 12 06:26:54 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 223632 kb
Host smart-2e191a15-f7ff-4e23-89f8-dcfba6f42142
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=861125817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.861125817 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.3297997298
Short name T236
Test name
Test status
Simulation time 3764492274 ps
CPU time 23.81 seconds
Started Aug 12 06:26:58 PM PDT 24
Finished Aug 12 06:27:22 PM PDT 24
Peak memory 223736 kb
Host smart-f68ca010-949b-4503-b723-f3d17fba6b1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3297997298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3297997298 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.797354605
Short name T353
Test name
Test status
Simulation time 13431924259 ps
CPU time 293.77 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:31:53 PM PDT 24
Peak memory 329416 kb
Host smart-c90d9794-4f2a-4de9-9201-a1030d64a002
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797354605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.79
7354605 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.139616080
Short name T514
Test name
Test status
Simulation time 9433791480 ps
CPU time 349.93 seconds
Started Aug 12 06:26:51 PM PDT 24
Finished Aug 12 06:32:41 PM PDT 24
Peak memory 373432 kb
Host smart-a60cf0ce-4867-4baa-839b-3bcd03ba0421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139616080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.139616080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2191734649
Short name T627
Test name
Test status
Simulation time 3614414067 ps
CPU time 8.6 seconds
Started Aug 12 06:27:00 PM PDT 24
Finished Aug 12 06:27:08 PM PDT 24
Peak memory 217844 kb
Host smart-72bc3b28-4632-46e1-ac9c-9227770085f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191734649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2191734649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.2036935125
Short name T628
Test name
Test status
Simulation time 61317769 ps
CPU time 1.97 seconds
Started Aug 12 06:26:52 PM PDT 24
Finished Aug 12 06:26:55 PM PDT 24
Peak memory 217040 kb
Host smart-a4a40904-cda9-41cc-b877-e89751e25a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036935125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2036935125 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.3320341203
Short name T719
Test name
Test status
Simulation time 51849237474 ps
CPU time 1504.42 seconds
Started Aug 12 06:26:48 PM PDT 24
Finished Aug 12 06:51:53 PM PDT 24
Peak memory 1125292 kb
Host smart-3696bccc-8bdf-42d5-9d5e-6c4e8ff82cc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320341203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.3320341203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1789433878
Short name T286
Test name
Test status
Simulation time 1384526000 ps
CPU time 13.91 seconds
Started Aug 12 06:26:58 PM PDT 24
Finished Aug 12 06:27:12 PM PDT 24
Peak memory 225328 kb
Host smart-87c1dfdb-9800-4f57-8b0b-fd3dc6d22135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789433878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1789433878 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.2409847738
Short name T405
Test name
Test status
Simulation time 449565676 ps
CPU time 8.97 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:26:55 PM PDT 24
Peak memory 217836 kb
Host smart-a2e75a99-1a65-441b-b5a8-b941080707b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409847738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2409847738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.2888619578
Short name T365
Test name
Test status
Simulation time 48089597413 ps
CPU time 1289.46 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:48:27 PM PDT 24
Peak memory 1236788 kb
Host smart-e2f80dac-1f13-4cae-a4ef-3fcc791f4cb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2888619578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2888619578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1804622368
Short name T521
Test name
Test status
Simulation time 43228752 ps
CPU time 0.79 seconds
Started Aug 12 06:26:54 PM PDT 24
Finished Aug 12 06:26:54 PM PDT 24
Peak memory 205056 kb
Host smart-70a9d9e1-7a94-4000-b9a8-fb0d74eb8a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804622368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1804622368 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.719250763
Short name T466
Test name
Test status
Simulation time 10246424217 ps
CPU time 205.4 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:30:24 PM PDT 24
Peak memory 415616 kb
Host smart-3bf03e14-52d8-42df-9608-9dc6c331d748
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719250763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.719250763 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.92969589
Short name T183
Test name
Test status
Simulation time 18316492858 ps
CPU time 599.65 seconds
Started Aug 12 06:26:55 PM PDT 24
Finished Aug 12 06:36:55 PM PDT 24
Peak memory 244044 kb
Host smart-dd1f7b0c-7156-4afa-b06f-bbc6dcf349ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92969589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.92969589 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.548620855
Short name T251
Test name
Test status
Simulation time 2546708596 ps
CPU time 32.76 seconds
Started Aug 12 06:26:45 PM PDT 24
Finished Aug 12 06:27:18 PM PDT 24
Peak memory 223744 kb
Host smart-39d33e3c-861f-4380-827c-ff9c1509fc3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=548620855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.548620855 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.2302929222
Short name T212
Test name
Test status
Simulation time 3026044174 ps
CPU time 17.13 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 223724 kb
Host smart-c1e08503-e6c7-43d8-b9c3-ec24589e36e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2302929222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2302929222 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.4152586286
Short name T36
Test name
Test status
Simulation time 7748798661 ps
CPU time 161.39 seconds
Started Aug 12 06:27:10 PM PDT 24
Finished Aug 12 06:29:51 PM PDT 24
Peak memory 368668 kb
Host smart-0ce75052-218b-4deb-8ed4-ccca64ffe789
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152586286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.4
152586286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.3755105947
Short name T684
Test name
Test status
Simulation time 4085339737 ps
CPU time 75.35 seconds
Started Aug 12 06:27:03 PM PDT 24
Finished Aug 12 06:28:19 PM PDT 24
Peak memory 264936 kb
Host smart-6ca4853f-6653-4649-9627-252f035f4c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755105947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3755105947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.3197602604
Short name T56
Test name
Test status
Simulation time 209016429 ps
CPU time 1.79 seconds
Started Aug 12 06:26:52 PM PDT 24
Finished Aug 12 06:26:54 PM PDT 24
Peak memory 217688 kb
Host smart-762782b5-b474-423b-9221-51261766a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197602604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3197602604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.2825253824
Short name T361
Test name
Test status
Simulation time 8687299228 ps
CPU time 326.44 seconds
Started Aug 12 06:26:53 PM PDT 24
Finished Aug 12 06:32:19 PM PDT 24
Peak memory 628340 kb
Host smart-24b036b0-81a0-4abe-971f-ea49f17ebfc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825253824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.2825253824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.2732875365
Short name T196
Test name
Test status
Simulation time 11694322395 ps
CPU time 51.95 seconds
Started Aug 12 06:26:58 PM PDT 24
Finished Aug 12 06:27:50 PM PDT 24
Peak memory 266432 kb
Host smart-c167de36-4b99-40c3-9994-8c0c14b85514
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732875365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2732875365 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.2088054878
Short name T517
Test name
Test status
Simulation time 955820062 ps
CPU time 47.81 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 217996 kb
Host smart-9e8d4c6c-5416-495b-9230-54d701b25a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088054878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2088054878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1586504823
Short name T630
Test name
Test status
Simulation time 9641028409 ps
CPU time 300.04 seconds
Started Aug 12 06:26:55 PM PDT 24
Finished Aug 12 06:31:56 PM PDT 24
Peak memory 348428 kb
Host smart-2bcd1795-85e6-45cb-ac78-574ddb10800c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1586504823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1586504823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_alert_test.583530956
Short name T271
Test name
Test status
Simulation time 13217476 ps
CPU time 0.78 seconds
Started Aug 12 06:26:53 PM PDT 24
Finished Aug 12 06:26:54 PM PDT 24
Peak memory 205092 kb
Host smart-c69882b6-3453-4d48-a66f-10e506d4beb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583530956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.583530956 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2750081428
Short name T621
Test name
Test status
Simulation time 3563324909 ps
CPU time 240.16 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:31:09 PM PDT 24
Peak memory 306272 kb
Host smart-fde048da-d9cf-46e3-9f29-b8e1d5bc4854
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750081428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2750081428 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.18792179
Short name T645
Test name
Test status
Simulation time 8768338141 ps
CPU time 793.97 seconds
Started Aug 12 06:26:54 PM PDT 24
Finished Aug 12 06:40:08 PM PDT 24
Peak memory 241496 kb
Host smart-03f0e17c-56e1-4e63-97cc-145c6522a3dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18792179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.18792179 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.482381025
Short name T693
Test name
Test status
Simulation time 239392778 ps
CPU time 8.45 seconds
Started Aug 12 06:27:00 PM PDT 24
Finished Aug 12 06:27:08 PM PDT 24
Peak memory 223660 kb
Host smart-e2e29e3f-4196-42d4-ba6e-178e03d4cb44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=482381025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.482381025 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.281678993
Short name T616
Test name
Test status
Simulation time 459573256 ps
CPU time 8.29 seconds
Started Aug 12 06:26:51 PM PDT 24
Finished Aug 12 06:26:59 PM PDT 24
Peak memory 223568 kb
Host smart-7daeb05e-e2bf-4809-a03b-f893f9d6bb43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281678993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.281678993 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.191553821
Short name T694
Test name
Test status
Simulation time 6767361785 ps
CPU time 54.39 seconds
Started Aug 12 06:26:55 PM PDT 24
Finished Aug 12 06:27:49 PM PDT 24
Peak memory 264420 kb
Host smart-97b84952-e4bc-4c1f-a4c6-499b8520c881
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191553821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.19
1553821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.3904598560
Short name T371
Test name
Test status
Simulation time 97702998535 ps
CPU time 399.6 seconds
Started Aug 12 06:27:03 PM PDT 24
Finished Aug 12 06:33:43 PM PDT 24
Peak memory 555332 kb
Host smart-c7564b92-def4-4d2d-bfdc-7497f6797ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904598560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3904598560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.331418279
Short name T321
Test name
Test status
Simulation time 15001722255 ps
CPU time 11.74 seconds
Started Aug 12 06:26:52 PM PDT 24
Finished Aug 12 06:27:04 PM PDT 24
Peak memory 218020 kb
Host smart-c9a82b9f-9f1f-47df-8e35-e0a452685f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331418279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.331418279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.1716534786
Short name T31
Test name
Test status
Simulation time 75206261 ps
CPU time 1.32 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:26:59 PM PDT 24
Peak memory 218872 kb
Host smart-2ed94920-e1ee-4611-83c0-704561d8325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716534786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1716534786 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3759009516
Short name T626
Test name
Test status
Simulation time 78561642881 ps
CPU time 538.8 seconds
Started Aug 12 06:26:56 PM PDT 24
Finished Aug 12 06:35:55 PM PDT 24
Peak memory 926020 kb
Host smart-7a7e8932-a799-4e1e-a013-210d94194bb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759009516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3759009516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3482416976
Short name T71
Test name
Test status
Simulation time 89371577542 ps
CPU time 329.86 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:32:27 PM PDT 24
Peak memory 510332 kb
Host smart-118cc113-1436-427a-9183-162dc72945d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482416976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3482416976 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.501300083
Short name T655
Test name
Test status
Simulation time 4558395256 ps
CPU time 23.77 seconds
Started Aug 12 06:26:53 PM PDT 24
Finished Aug 12 06:27:17 PM PDT 24
Peak memory 217920 kb
Host smart-ae9107bc-4a60-42b8-a5cc-21f770419755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501300083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.501300083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_app.1266434074
Short name T503
Test name
Test status
Simulation time 14244210905 ps
CPU time 307.82 seconds
Started Aug 12 06:27:09 PM PDT 24
Finished Aug 12 06:32:17 PM PDT 24
Peak memory 491272 kb
Host smart-4824a026-52ba-4783-905c-3ef0acc6d2ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266434074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1266434074 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.1862726324
Short name T233
Test name
Test status
Simulation time 41370800960 ps
CPU time 397.55 seconds
Started Aug 12 06:26:56 PM PDT 24
Finished Aug 12 06:33:33 PM PDT 24
Peak memory 239644 kb
Host smart-c289ee9d-438a-45cf-a5ce-45af554c372b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862726324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.186272632
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.658266310
Short name T479
Test name
Test status
Simulation time 780739954 ps
CPU time 24.73 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:27:24 PM PDT 24
Peak memory 223656 kb
Host smart-8cc20307-aa56-476d-90aa-f339ecea0cd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=658266310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.658266310 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2701640105
Short name T556
Test name
Test status
Simulation time 150840723 ps
CPU time 10.61 seconds
Started Aug 12 06:26:58 PM PDT 24
Finished Aug 12 06:27:09 PM PDT 24
Peak memory 219800 kb
Host smart-47eb4a7f-3ed0-4421-aac6-896e616b0948
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2701640105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2701640105 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.4174536482
Short name T64
Test name
Test status
Simulation time 9442656891 ps
CPU time 121.56 seconds
Started Aug 12 06:26:54 PM PDT 24
Finished Aug 12 06:28:56 PM PDT 24
Peak memory 275564 kb
Host smart-121e814b-ff22-4c14-9e9f-269d5ac1a14a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174536482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.4
174536482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.1053665270
Short name T28
Test name
Test status
Simulation time 705443068 ps
CPU time 45.98 seconds
Started Aug 12 06:26:55 PM PDT 24
Finished Aug 12 06:27:41 PM PDT 24
Peak memory 256648 kb
Host smart-a82ebddc-9fbb-42b2-800f-7353afa55634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053665270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1053665270 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.705598250
Short name T596
Test name
Test status
Simulation time 7909050410 ps
CPU time 11.56 seconds
Started Aug 12 06:27:04 PM PDT 24
Finished Aug 12 06:27:16 PM PDT 24
Peak memory 217880 kb
Host smart-48897507-9a06-42dd-b77c-6a2c8c2d97d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705598250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.705598250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3660310629
Short name T277
Test name
Test status
Simulation time 52792219545 ps
CPU time 2545.12 seconds
Started Aug 12 06:26:53 PM PDT 24
Finished Aug 12 07:09:18 PM PDT 24
Peak memory 1563900 kb
Host smart-8a4fb855-b408-429c-a1c9-f40ba17e6373
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660310629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3660310629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.3965400677
Short name T715
Test name
Test status
Simulation time 8964161399 ps
CPU time 148.12 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:29:36 PM PDT 24
Peak memory 283412 kb
Host smart-08d09488-0947-4cfb-b08b-b0e4744c5401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965400677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3965400677 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.3666530380
Short name T572
Test name
Test status
Simulation time 929185349 ps
CPU time 8.38 seconds
Started Aug 12 06:26:56 PM PDT 24
Finished Aug 12 06:27:05 PM PDT 24
Peak memory 220344 kb
Host smart-ff22e6fb-1fba-4fbf-9bdc-bf40f3c26fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666530380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3666530380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_alert_test.3850253484
Short name T529
Test name
Test status
Simulation time 29781890 ps
CPU time 0.72 seconds
Started Aug 12 06:27:05 PM PDT 24
Finished Aug 12 06:27:06 PM PDT 24
Peak memory 205088 kb
Host smart-d063da93-a8ac-49fd-9e7d-d3fc9609e2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850253484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3850253484 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.494389190
Short name T281
Test name
Test status
Simulation time 3307036872 ps
CPU time 212.12 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:30:31 PM PDT 24
Peak memory 308984 kb
Host smart-526dabf2-1a2d-4ba0-8c37-6637819392d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494389190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.494389190 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.619366210
Short name T446
Test name
Test status
Simulation time 27949657901 ps
CPU time 853.73 seconds
Started Aug 12 06:26:56 PM PDT 24
Finished Aug 12 06:41:10 PM PDT 24
Peak memory 242900 kb
Host smart-1c593be4-9957-4fb8-adec-2797034b9e2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619366210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.619366210
+enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.3903727501
Short name T344
Test name
Test status
Simulation time 407421859 ps
CPU time 15.38 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:27:24 PM PDT 24
Peak memory 219012 kb
Host smart-16e93a41-b29c-4eb4-86ad-0f164ed2ab36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3903727501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3903727501 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.408090431
Short name T192
Test name
Test status
Simulation time 2972013719 ps
CPU time 10.71 seconds
Started Aug 12 06:27:10 PM PDT 24
Finished Aug 12 06:27:21 PM PDT 24
Peak memory 217500 kb
Host smart-85457dcf-d25b-430e-a99f-4df2542d19cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=408090431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.408090431 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.2392207517
Short name T552
Test name
Test status
Simulation time 4673968720 ps
CPU time 130.2 seconds
Started Aug 12 06:27:09 PM PDT 24
Finished Aug 12 06:29:20 PM PDT 24
Peak memory 268288 kb
Host smart-559fdf98-d2ec-49f4-84d3-2bc5bf3f97af
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392207517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2
392207517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_key_error.990660503
Short name T516
Test name
Test status
Simulation time 900327965 ps
CPU time 4.66 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:27:12 PM PDT 24
Peak memory 217468 kb
Host smart-0d9a816d-2761-4964-88d9-28f77c762aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990660503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.990660503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.457118026
Short name T73
Test name
Test status
Simulation time 165007661 ps
CPU time 1.33 seconds
Started Aug 12 06:27:00 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 217188 kb
Host smart-615684cb-1aa0-4fb5-9490-7c982e04b93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457118026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.457118026 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.3917340416
Short name T574
Test name
Test status
Simulation time 25804767644 ps
CPU time 3205.47 seconds
Started Aug 12 06:26:58 PM PDT 24
Finished Aug 12 07:20:24 PM PDT 24
Peak memory 1799160 kb
Host smart-6dad5206-9d90-450c-b88e-e6613d6c4782
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917340416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.3917340416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.3234418278
Short name T423
Test name
Test status
Simulation time 17306284688 ps
CPU time 92.46 seconds
Started Aug 12 06:26:55 PM PDT 24
Finished Aug 12 06:28:28 PM PDT 24
Peak memory 298556 kb
Host smart-681eea61-846a-4f2d-bc4e-7d85c13b1411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234418278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3234418278 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.2994216922
Short name T191
Test name
Test status
Simulation time 1036794470 ps
CPU time 26.24 seconds
Started Aug 12 06:27:03 PM PDT 24
Finished Aug 12 06:27:30 PM PDT 24
Peak memory 218148 kb
Host smart-0372dc49-f986-4723-a17f-ca6faeb034a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994216922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2994216922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.2878962210
Short name T206
Test name
Test status
Simulation time 329141961 ps
CPU time 2.12 seconds
Started Aug 12 06:26:56 PM PDT 24
Finished Aug 12 06:26:58 PM PDT 24
Peak memory 218552 kb
Host smart-ece615d7-8200-465c-afb0-707ff2c8d18a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2878962210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2878962210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2551035696
Short name T313
Test name
Test status
Simulation time 14931545 ps
CPU time 0.78 seconds
Started Aug 12 06:27:11 PM PDT 24
Finished Aug 12 06:27:12 PM PDT 24
Peak memory 205084 kb
Host smart-0d062df7-4e0b-4322-9373-91c012f410ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551035696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2551035696 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.858372597
Short name T527
Test name
Test status
Simulation time 20393851364 ps
CPU time 53.9 seconds
Started Aug 12 06:27:05 PM PDT 24
Finished Aug 12 06:27:59 PM PDT 24
Peak memory 260648 kb
Host smart-2d3a14ea-91bb-4846-8147-9169f99b5ed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858372597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.858372597 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.1892416011
Short name T225
Test name
Test status
Simulation time 85598011144 ps
CPU time 592.25 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:37:05 PM PDT 24
Peak memory 237648 kb
Host smart-33c68aa5-98ea-41c1-a55d-46acd35919ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892416011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.189241601
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1554254601
Short name T453
Test name
Test status
Simulation time 644056050 ps
CPU time 17.18 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:27:16 PM PDT 24
Peak memory 223572 kb
Host smart-0921e4b4-b4a3-4962-89bc-21638b99ca6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1554254601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1554254601 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.4011473245
Short name T175
Test name
Test status
Simulation time 450057047 ps
CPU time 31.65 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:27:38 PM PDT 24
Peak memory 220640 kb
Host smart-70432dd1-1b04-492f-a4ae-997067e8852e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4011473245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4011473245 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.4079256616
Short name T557
Test name
Test status
Simulation time 6708049861 ps
CPU time 34.21 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 228312 kb
Host smart-caaa8a95-b103-43fa-a1e4-ce988f9923af
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079256616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.4
079256616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.2781516001
Short name T145
Test name
Test status
Simulation time 3201307825 ps
CPU time 35.89 seconds
Started Aug 12 06:26:58 PM PDT 24
Finished Aug 12 06:27:34 PM PDT 24
Peak memory 254000 kb
Host smart-8aee4c92-f221-4039-8920-b9e42c0c6a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781516001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2781516001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.3782464383
Short name T357
Test name
Test status
Simulation time 1444673488 ps
CPU time 7.96 seconds
Started Aug 12 06:27:02 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 217824 kb
Host smart-128c7ce6-a3d6-4c0d-99fa-f79fab82423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782464383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3782464383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3181666703
Short name T498
Test name
Test status
Simulation time 24947104712 ps
CPU time 3134.8 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 07:19:16 PM PDT 24
Peak memory 1689084 kb
Host smart-649c34f5-25ff-41c4-a32e-449b949d02b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181666703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3181666703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2931141047
Short name T249
Test name
Test status
Simulation time 3656850100 ps
CPU time 94.88 seconds
Started Aug 12 06:26:56 PM PDT 24
Finished Aug 12 06:28:31 PM PDT 24
Peak memory 315536 kb
Host smart-a23b7b27-798d-47fa-a8b4-3a65c65e736f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931141047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2931141047 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.360028222
Short name T328
Test name
Test status
Simulation time 2530897547 ps
CPU time 39.57 seconds
Started Aug 12 06:27:05 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 217980 kb
Host smart-852d38a1-ac50-4c5f-901b-fdb3cbc1d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360028222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.360028222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.3805767072
Short name T445
Test name
Test status
Simulation time 10737272468 ps
CPU time 382.57 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:33:24 PM PDT 24
Peak memory 314428 kb
Host smart-90890b06-645a-4cd6-b690-1309af73ec45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3805767072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3805767072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_alert_test.3793777943
Short name T46
Test name
Test status
Simulation time 66691415 ps
CPU time 0.84 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 205036 kb
Host smart-218be83c-0d97-42e0-9c46-59dc21b9622d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793777943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3793777943 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.4015626347
Short name T427
Test name
Test status
Simulation time 4483532211 ps
CPU time 51.77 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:27:51 PM PDT 24
Peak memory 265880 kb
Host smart-3a619c42-dab9-4468-a9c6-773b5b624c0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015626347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.4015626347 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.2974850915
Short name T526
Test name
Test status
Simulation time 2768999305 ps
CPU time 255.61 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:31:16 PM PDT 24
Peak memory 229140 kb
Host smart-0397c844-fff5-4362-9f0c-197382d8b5be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974850915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.297485091
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.2834463585
Short name T567
Test name
Test status
Simulation time 1125549942 ps
CPU time 28.34 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:27:27 PM PDT 24
Peak memory 220300 kb
Host smart-2c579185-2201-4c2f-897a-1a84df60c706
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2834463585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2834463585 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.3829973997
Short name T171
Test name
Test status
Simulation time 1488236947 ps
CPU time 26.71 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:27:34 PM PDT 24
Peak memory 223632 kb
Host smart-7b52d192-e589-4f97-bd0b-af63c0ccc4f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3829973997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3829973997 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.3637100564
Short name T293
Test name
Test status
Simulation time 19930321352 ps
CPU time 280.78 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:31:42 PM PDT 24
Peak memory 449164 kb
Host smart-42333ca5-f724-41a2-9dcb-226c14b97be4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637100564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3
637100564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.3435183852
Short name T144
Test name
Test status
Simulation time 3837271678 ps
CPU time 286.37 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:31:48 PM PDT 24
Peak memory 351772 kb
Host smart-f4f0bbc7-608a-4e8b-8072-28bef3dfa9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435183852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3435183852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.4272116839
Short name T511
Test name
Test status
Simulation time 239478703 ps
CPU time 2 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:27:09 PM PDT 24
Peak memory 217808 kb
Host smart-34294da9-9c92-41a8-ad96-d179bc38b3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272116839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.4272116839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.592922952
Short name T464
Test name
Test status
Simulation time 202279108 ps
CPU time 1.56 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 217788 kb
Host smart-81f6fb6c-252b-4c14-9eb3-72e785678216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592922952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.592922952 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_sideload.314776071
Short name T338
Test name
Test status
Simulation time 4209969176 ps
CPU time 341.81 seconds
Started Aug 12 06:26:58 PM PDT 24
Finished Aug 12 06:32:40 PM PDT 24
Peak memory 357348 kb
Host smart-38b7fd35-e492-4061-a0bd-b122a5883019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314776071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.314776071 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.3487438342
Short name T547
Test name
Test status
Simulation time 353567195 ps
CPU time 8.64 seconds
Started Aug 12 06:27:05 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 217732 kb
Host smart-68614a1a-3e90-45e4-a168-2a5ebf3e8d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487438342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3487438342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.1531310013
Short name T246
Test name
Test status
Simulation time 17323623188 ps
CPU time 746.93 seconds
Started Aug 12 06:27:10 PM PDT 24
Finished Aug 12 06:39:37 PM PDT 24
Peak memory 604516 kb
Host smart-dad1b5e3-e323-4cf3-82e2-232d07fd5824
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1531310013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1531310013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2994781936
Short name T632
Test name
Test status
Simulation time 97866598 ps
CPU time 0.75 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:27:08 PM PDT 24
Peak memory 205068 kb
Host smart-db3eb9b3-66c7-48b6-9aee-ce3ac2c72d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994781936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2994781936 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.2079716870
Short name T593
Test name
Test status
Simulation time 8436365354 ps
CPU time 146.55 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:29:33 PM PDT 24
Peak memory 351132 kb
Host smart-456425b9-abf2-4886-96dd-d730004eaace
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079716870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2079716870 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.3902592813
Short name T706
Test name
Test status
Simulation time 7303716466 ps
CPU time 677.48 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:38:25 PM PDT 24
Peak memory 238696 kb
Host smart-5f249bdb-3f81-449c-b706-e844c69dc902
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902592813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.390259281
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1401823366
Short name T349
Test name
Test status
Simulation time 579132003 ps
CPU time 29.55 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:27:42 PM PDT 24
Peak memory 223628 kb
Host smart-6290096b-a3e8-4f7c-b288-962b9efd5248
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1401823366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1401823366 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.1414994726
Short name T705
Test name
Test status
Simulation time 1791636350 ps
CPU time 37.74 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 223620 kb
Host smart-2f3acd66-fa5a-4cb8-8e60-dd09a66e0c16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414994726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1414994726 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.821703119
Short name T548
Test name
Test status
Simulation time 2993125566 ps
CPU time 13.77 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:27:15 PM PDT 24
Peak memory 221076 kb
Host smart-3b4d32ef-d152-400b-a509-0cc6f7dc0fbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821703119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.82
1703119 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.4170308938
Short name T74
Test name
Test status
Simulation time 3142409813 ps
CPU time 235 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:31:01 PM PDT 24
Peak memory 324984 kb
Host smart-d4ae0250-90b1-4e2b-9ff3-d514e56eb0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170308938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.4170308938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.3607558991
Short name T59
Test name
Test status
Simulation time 2661907723 ps
CPU time 7.37 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:27:08 PM PDT 24
Peak memory 217668 kb
Host smart-7def9345-846d-4bd6-888e-6b52dea5b4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607558991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3607558991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.230259827
Short name T87
Test name
Test status
Simulation time 61345790 ps
CPU time 1.37 seconds
Started Aug 12 06:27:00 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 218816 kb
Host smart-e97ad7ff-6fc2-4e3e-8285-0e30f6045fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230259827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.230259827 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.3650541587
Short name T604
Test name
Test status
Simulation time 39761664505 ps
CPU time 1782.31 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:56:49 PM PDT 24
Peak memory 2041988 kb
Host smart-66563f16-0ebd-4609-808b-7275da8976b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650541587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.3650541587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.207451119
Short name T697
Test name
Test status
Simulation time 19020013802 ps
CPU time 428.87 seconds
Started Aug 12 06:27:03 PM PDT 24
Finished Aug 12 06:34:12 PM PDT 24
Peak memory 601840 kb
Host smart-f01e542a-4abf-42ea-9a51-0d9dcb27fdb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207451119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.207451119 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.2289327678
Short name T65
Test name
Test status
Simulation time 521119398 ps
CPU time 2.58 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 217756 kb
Host smart-4821ca3c-8dc4-4700-87fe-f22cf9c5d532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289327678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2289327678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.359515192
Short name T101
Test name
Test status
Simulation time 398307599 ps
CPU time 13.75 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:27:13 PM PDT 24
Peak memory 220480 kb
Host smart-20aa1f1a-bc84-4dcf-b41c-5fef4247a892
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=359515192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.359515192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2067799051
Short name T515
Test name
Test status
Simulation time 105744319 ps
CPU time 0.86 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:27:20 PM PDT 24
Peak memory 205112 kb
Host smart-331aac53-faad-4741-91c0-686088198802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067799051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2067799051 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.2323350312
Short name T659
Test name
Test status
Simulation time 4048154665 ps
CPU time 43.39 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:27:44 PM PDT 24
Peak memory 236768 kb
Host smart-922488b6-368b-4a10-8f39-c15beaca7fa6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323350312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2323350312 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.910710179
Short name T550
Test name
Test status
Simulation time 13125435267 ps
CPU time 236.49 seconds
Started Aug 12 06:26:59 PM PDT 24
Finished Aug 12 06:30:55 PM PDT 24
Peak memory 230368 kb
Host smart-bfc07097-267f-49dd-a987-fd85781a0eaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910710179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.910710179
+enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3096897828
Short name T179
Test name
Test status
Simulation time 538116093 ps
CPU time 19.78 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:27:21 PM PDT 24
Peak memory 223660 kb
Host smart-8e966f76-f8f8-4e85-be71-ba65120b5789
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3096897828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3096897828 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.979558760
Short name T452
Test name
Test status
Simulation time 1648776809 ps
CPU time 11.55 seconds
Started Aug 12 06:27:11 PM PDT 24
Finished Aug 12 06:27:23 PM PDT 24
Peak memory 218644 kb
Host smart-a7676989-186c-4e38-9538-a7da12975de7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=979558760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.979558760 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.952763463
Short name T282
Test name
Test status
Simulation time 21515387137 ps
CPU time 369.69 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:33:07 PM PDT 24
Peak memory 539244 kb
Host smart-222dca6f-ca4c-453f-8827-3cce0cf897a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952763463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.95
2763463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.2770277177
Short name T512
Test name
Test status
Simulation time 14200094930 ps
CPU time 81.17 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:28:27 PM PDT 24
Peak memory 295000 kb
Host smart-8cc743b0-2844-41e7-b9f3-62ecbc0399e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770277177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2770277177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.402691587
Short name T689
Test name
Test status
Simulation time 1114230722 ps
CPU time 5.99 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:27:18 PM PDT 24
Peak memory 217488 kb
Host smart-a4c33f64-63f8-4c8d-be03-bbe2994585f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402691587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.402691587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.3042003496
Short name T33
Test name
Test status
Simulation time 157831428 ps
CPU time 1.27 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:27:18 PM PDT 24
Peak memory 219224 kb
Host smart-a0250bb6-75c1-4789-84ec-49584abc0e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042003496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3042003496 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3310062129
Short name T314
Test name
Test status
Simulation time 44353902617 ps
CPU time 150.58 seconds
Started Aug 12 06:27:01 PM PDT 24
Finished Aug 12 06:29:31 PM PDT 24
Peak memory 450788 kb
Host smart-f865c476-bcd2-4832-a04f-7bdc78785d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310062129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3310062129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2782014895
Short name T584
Test name
Test status
Simulation time 5540103001 ps
CPU time 91.12 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:28:39 PM PDT 24
Peak memory 259260 kb
Host smart-160a99c8-319e-457c-a838-67788afe1842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782014895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2782014895 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.2206110570
Short name T671
Test name
Test status
Simulation time 85726972 ps
CPU time 2.36 seconds
Started Aug 12 06:26:57 PM PDT 24
Finished Aug 12 06:27:00 PM PDT 24
Peak memory 218036 kb
Host smart-865209da-0950-47f2-a9bd-1f0e752c6fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206110570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2206110570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.1353231973
Short name T492
Test name
Test status
Simulation time 26730099664 ps
CPU time 636.31 seconds
Started Aug 12 06:27:09 PM PDT 24
Finished Aug 12 06:37:46 PM PDT 24
Peak memory 826048 kb
Host smart-e0e102ca-910b-45c2-a06a-6c2d84f1c81d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1353231973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1353231973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_alert_test.2609597250
Short name T450
Test name
Test status
Simulation time 42322289 ps
CPU time 0.77 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:26:16 PM PDT 24
Peak memory 205116 kb
Host smart-a6babff5-133b-46ee-af16-9a5fe17f9a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609597250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2609597250 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.4118037698
Short name T508
Test name
Test status
Simulation time 1500709239 ps
CPU time 29.54 seconds
Started Aug 12 06:26:26 PM PDT 24
Finished Aug 12 06:26:55 PM PDT 24
Peak memory 247512 kb
Host smart-0fa8a5d9-2479-4930-aae8-9d8a128b8b06
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118037698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4118037698 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.373016975
Short name T642
Test name
Test status
Simulation time 95623118639 ps
CPU time 300.31 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:31:37 PM PDT 24
Peak memory 451912 kb
Host smart-ad84c8d0-ee8d-411c-851b-04c3d5c91a35
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373016975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_part
ial_data.373016975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.703273204
Short name T430
Test name
Test status
Simulation time 10490736843 ps
CPU time 741.44 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:38:36 PM PDT 24
Peak memory 241372 kb
Host smart-7e665a88-d86e-49ff-9e7a-c9035e00807a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703273204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.703273204 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1580148691
Short name T531
Test name
Test status
Simulation time 3812877662 ps
CPU time 15.3 seconds
Started Aug 12 06:26:25 PM PDT 24
Finished Aug 12 06:26:41 PM PDT 24
Peak memory 223716 kb
Host smart-1daa78f7-faa8-4368-8f02-ae59407fa3ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1580148691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1580148691 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.2160375418
Short name T252
Test name
Test status
Simulation time 6390662098 ps
CPU time 26.64 seconds
Started Aug 12 06:26:18 PM PDT 24
Finished Aug 12 06:26:45 PM PDT 24
Peak memory 223712 kb
Host smart-1fc9f9a8-7eeb-4c01-85f7-42025bf58ea9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2160375418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2160375418 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.1747494152
Short name T510
Test name
Test status
Simulation time 76975981174 ps
CPU time 42.46 seconds
Started Aug 12 06:26:27 PM PDT 24
Finished Aug 12 06:27:10 PM PDT 24
Peak memory 218460 kb
Host smart-b062bf11-3e44-4672-b07c-7516b45c400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747494152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1747494152 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3528934073
Short name T691
Test name
Test status
Simulation time 15585168561 ps
CPU time 81.66 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:27:58 PM PDT 24
Peak memory 289472 kb
Host smart-6c1e9486-a6cf-4cee-b080-6863bcab7555
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528934073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.35
28934073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_key_error.3021972178
Short name T701
Test name
Test status
Simulation time 634293545 ps
CPU time 1.6 seconds
Started Aug 12 06:26:27 PM PDT 24
Finished Aug 12 06:26:29 PM PDT 24
Peak memory 217560 kb
Host smart-c298ed62-44a2-4870-b07a-bc5c9e7f436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021972178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3021972178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2081254962
Short name T398
Test name
Test status
Simulation time 53163686 ps
CPU time 1.47 seconds
Started Aug 12 06:26:28 PM PDT 24
Finished Aug 12 06:26:30 PM PDT 24
Peak memory 217820 kb
Host smart-4f230af1-c0e1-4bc3-bb93-0742f1fd4889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081254962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2081254962 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.1718312189
Short name T425
Test name
Test status
Simulation time 1624020426 ps
CPU time 144.31 seconds
Started Aug 12 06:26:17 PM PDT 24
Finished Aug 12 06:28:41 PM PDT 24
Peak memory 305636 kb
Host smart-4909f747-e2f0-427f-9800-3edf23d52448
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718312189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.1718312189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.2631767022
Short name T325
Test name
Test status
Simulation time 44397662616 ps
CPU time 352.41 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:32:09 PM PDT 24
Peak memory 510280 kb
Host smart-88df6aca-f395-4abb-9dbc-117bff16bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631767022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2631767022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2619039002
Short name T12
Test name
Test status
Simulation time 6603281211 ps
CPU time 50.83 seconds
Started Aug 12 06:26:34 PM PDT 24
Finished Aug 12 06:27:25 PM PDT 24
Peak memory 253204 kb
Host smart-ad960cb7-0670-4a91-b097-ed9b0ea1db41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619039002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2619039002 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1263447136
Short name T522
Test name
Test status
Simulation time 16615628598 ps
CPU time 336.02 seconds
Started Aug 12 06:26:36 PM PDT 24
Finished Aug 12 06:32:12 PM PDT 24
Peak memory 364128 kb
Host smart-68dd45aa-a3fc-4f90-afc2-01f9da35b09b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263447136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1263447136 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3865793695
Short name T16
Test name
Test status
Simulation time 987811889 ps
CPU time 21.75 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:26:38 PM PDT 24
Peak memory 222508 kb
Host smart-67c448a9-b264-4348-85c5-260172d8d7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865793695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3865793695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.3899700658
Short name T533
Test name
Test status
Simulation time 3662847689 ps
CPU time 126.81 seconds
Started Aug 12 06:26:26 PM PDT 24
Finished Aug 12 06:28:33 PM PDT 24
Peak memory 310636 kb
Host smart-3a83bb06-3762-4858-b121-b5fdd857d520
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3899700658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3899700658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.465771805
Short name T597
Test name
Test status
Simulation time 59126025 ps
CPU time 2.17 seconds
Started Aug 12 06:26:26 PM PDT 24
Finished Aug 12 06:26:28 PM PDT 24
Peak memory 218120 kb
Host smart-d05d63f0-7548-46d5-ac5e-96d4232e68ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465771805 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.465771805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.57904898
Short name T14
Test name
Test status
Simulation time 416362148 ps
CPU time 2.41 seconds
Started Aug 12 06:26:35 PM PDT 24
Finished Aug 12 06:26:37 PM PDT 24
Peak memory 218128 kb
Host smart-d65e9a6c-db9e-46aa-83de-ad5c3fb0cc57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57904898 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.kmac_test_vectors_kmac_xof.57904898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.4229233892
Short name T85
Test name
Test status
Simulation time 17644125276 ps
CPU time 1715.14 seconds
Started Aug 12 06:26:34 PM PDT 24
Finished Aug 12 06:55:09 PM PDT 24
Peak memory 1172160 kb
Host smart-6f8c6b93-b7ce-47c9-91e6-74acb05e9192
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4229233892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.4229233892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3035390324
Short name T426
Test name
Test status
Simulation time 1466396921 ps
CPU time 30.19 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:26:45 PM PDT 24
Peak memory 218448 kb
Host smart-9b9a312c-ecfc-4fd3-b981-21ac133ccc13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3035390324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3035390324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2442831777
Short name T189
Test name
Test status
Simulation time 1955356167 ps
CPU time 29.73 seconds
Started Aug 12 06:26:30 PM PDT 24
Finished Aug 12 06:27:00 PM PDT 24
Peak memory 228392 kb
Host smart-abcaff90-322f-406b-8d77-6920af433df9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2442831777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2442831777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2143727527
Short name T377
Test name
Test status
Simulation time 96262136837 ps
CPU time 1430.98 seconds
Started Aug 12 06:26:33 PM PDT 24
Finished Aug 12 06:50:25 PM PDT 24
Peak memory 1686580 kb
Host smart-3a1235a4-645c-48aa-902d-6e836c44305b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2143727527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2143727527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.3592500821
Short name T334
Test name
Test status
Simulation time 354726720578 ps
CPU time 3347.54 seconds
Started Aug 12 06:26:22 PM PDT 24
Finished Aug 12 07:22:11 PM PDT 24
Peak memory 3609640 kb
Host smart-75a062ed-5d7f-4f52-9351-94c507fe8af8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3592500821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3592500821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.1988152754
Short name T648
Test name
Test status
Simulation time 7147318617 ps
CPU time 104.99 seconds
Started Aug 12 06:26:33 PM PDT 24
Finished Aug 12 06:28:18 PM PDT 24
Peak memory 252420 kb
Host smart-23967912-ec10-4257-a652-b7066c78f656
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1988152754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1988152754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3494497884
Short name T528
Test name
Test status
Simulation time 32238764 ps
CPU time 0.78 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:27:13 PM PDT 24
Peak memory 205088 kb
Host smart-47751cf7-962b-4ba4-8f94-e3f7886a4f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494497884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3494497884 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.548698845
Short name T454
Test name
Test status
Simulation time 6911042311 ps
CPU time 56.68 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:28:03 PM PDT 24
Peak memory 268376 kb
Host smart-aabf7da9-a583-4c3a-a707-26527c3e1aea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548698845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.548698845 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2236418045
Short name T518
Test name
Test status
Simulation time 14987705420 ps
CPU time 142.18 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:29:41 PM PDT 24
Peak memory 240392 kb
Host smart-98776a46-066c-4f97-87db-566d7a6e81fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236418045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.223641804
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.3316164877
Short name T657
Test name
Test status
Simulation time 13550659901 ps
CPU time 233.62 seconds
Started Aug 12 06:27:11 PM PDT 24
Finished Aug 12 06:31:05 PM PDT 24
Peak memory 433220 kb
Host smart-08f3ac70-f988-4141-ae3d-77c2a73092f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316164877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3
316164877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.707858022
Short name T455
Test name
Test status
Simulation time 7965460441 ps
CPU time 180.56 seconds
Started Aug 12 06:27:13 PM PDT 24
Finished Aug 12 06:30:14 PM PDT 24
Peak memory 408288 kb
Host smart-ae8dc40a-ccbf-4612-8635-c0e600f4d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707858022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.707858022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.1001669444
Short name T227
Test name
Test status
Simulation time 290559023 ps
CPU time 2.36 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:27:10 PM PDT 24
Peak memory 218908 kb
Host smart-4c75b50f-7a07-4354-9b04-56e851a1eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001669444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1001669444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.1350193485
Short name T499
Test name
Test status
Simulation time 36793851 ps
CPU time 1.28 seconds
Started Aug 12 06:27:10 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 218768 kb
Host smart-18868f00-4fc5-4ec2-b54f-36c83e2cb92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350193485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1350193485 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.449551855
Short name T207
Test name
Test status
Simulation time 43848990241 ps
CPU time 647.4 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:38:07 PM PDT 24
Peak memory 963184 kb
Host smart-33c1a044-c067-43fc-be56-9c770fc348c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449551855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an
d_output.449551855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.985700760
Short name T624
Test name
Test status
Simulation time 38892653745 ps
CPU time 235.64 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:31:11 PM PDT 24
Peak memory 454672 kb
Host smart-6c3ea024-fa7d-44b3-a62e-0a5f7d822f41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985700760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.985700760 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.2124426884
Short name T298
Test name
Test status
Simulation time 94290074 ps
CPU time 1.2 seconds
Started Aug 12 06:27:05 PM PDT 24
Finished Aug 12 06:27:06 PM PDT 24
Peak memory 218136 kb
Host smart-9ef9efe1-0245-42ab-8f0d-27e4331aaae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124426884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2124426884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2113606373
Short name T37
Test name
Test status
Simulation time 146866327231 ps
CPU time 1423.76 seconds
Started Aug 12 06:27:11 PM PDT 24
Finished Aug 12 06:50:55 PM PDT 24
Peak memory 1295668 kb
Host smart-42fc9afd-f353-4ea5-bf60-9b2d42297024
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2113606373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2113606373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_alert_test.446100425
Short name T712
Test name
Test status
Simulation time 27068398 ps
CPU time 0.81 seconds
Started Aug 12 06:27:13 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 205096 kb
Host smart-af1bc236-ea32-4cfb-b5b8-9b8828597103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446100425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.446100425 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.4078090367
Short name T485
Test name
Test status
Simulation time 36008272421 ps
CPU time 204.04 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:30:37 PM PDT 24
Peak memory 396660 kb
Host smart-02ea065c-368b-4cc5-b8dd-c8401c2772df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078090367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.4078090367 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.1840122087
Short name T222
Test name
Test status
Simulation time 1907457591 ps
CPU time 173.65 seconds
Started Aug 12 06:27:10 PM PDT 24
Finished Aug 12 06:30:04 PM PDT 24
Peak memory 226404 kb
Host smart-ec6a5f1a-c5dc-4393-bae6-c3d0355f23e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840122087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.184012208
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.1862170608
Short name T440
Test name
Test status
Simulation time 2134639653 ps
CPU time 66.69 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:28:14 PM PDT 24
Peak memory 246952 kb
Host smart-53002fd9-cffe-4b38-875e-1967415ee3de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862170608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1
862170608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.3415137559
Short name T142
Test name
Test status
Simulation time 9306872584 ps
CPU time 73.33 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:28:26 PM PDT 24
Peak memory 261380 kb
Host smart-6aea3f50-9874-4af3-a9c5-f6bc57424502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415137559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3415137559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.3817076371
Short name T534
Test name
Test status
Simulation time 5522188430 ps
CPU time 8.11 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 217956 kb
Host smart-636e5da0-782c-4195-98e6-263bd9486bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817076371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3817076371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.115138173
Short name T457
Test name
Test status
Simulation time 333433957 ps
CPU time 1.21 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 222952 kb
Host smart-a4b68849-91b0-497f-a312-e6fbcc7633fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115138173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.115138173 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.86992385
Short name T700
Test name
Test status
Simulation time 125238578320 ps
CPU time 3645.89 seconds
Started Aug 12 06:27:09 PM PDT 24
Finished Aug 12 07:27:56 PM PDT 24
Peak memory 1962924 kb
Host smart-023ab723-02c9-4319-b3b5-e7ed85cb666e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86992385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and
_output.86992385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.636088464
Short name T525
Test name
Test status
Simulation time 13180940693 ps
CPU time 306.72 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:32:13 PM PDT 24
Peak memory 504324 kb
Host smart-5aab9ad5-0d98-4c30-80c4-205038a9236d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636088464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.636088464 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.1919521124
Short name T565
Test name
Test status
Simulation time 203897779 ps
CPU time 7.43 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 217980 kb
Host smart-ff3c54e1-786a-4814-bd81-6148d653f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919521124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1919521124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.794742741
Short name T710
Test name
Test status
Simulation time 27372145696 ps
CPU time 570.19 seconds
Started Aug 12 06:27:08 PM PDT 24
Finished Aug 12 06:36:39 PM PDT 24
Peak memory 467816 kb
Host smart-438dec50-6360-4a7e-a0e0-71aebba9efb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=794742741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.794742741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2962101788
Short name T536
Test name
Test status
Simulation time 16639904 ps
CPU time 0.85 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:27:07 PM PDT 24
Peak memory 205064 kb
Host smart-99949f1c-b5c6-4d3b-9c2e-17394f2dd0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962101788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2962101788 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.2131395133
Short name T524
Test name
Test status
Simulation time 903419410 ps
CPU time 31.78 seconds
Started Aug 12 06:27:11 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 230884 kb
Host smart-108ad550-39d5-4ecd-8761-0ded0f95d86a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131395133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2131395133 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.3929024770
Short name T638
Test name
Test status
Simulation time 14191359852 ps
CPU time 551.72 seconds
Started Aug 12 06:27:20 PM PDT 24
Finished Aug 12 06:36:32 PM PDT 24
Peak memory 243484 kb
Host smart-169814da-2169-4796-8f87-0979f684fbe8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929024770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.392902477
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.154236555
Short name T102
Test name
Test status
Simulation time 698630712 ps
CPU time 12.32 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:27:18 PM PDT 24
Peak memory 218564 kb
Host smart-5f96cfa8-c3db-4fe8-a273-605a191ce6ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154236555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.15
4236555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.1108754178
Short name T610
Test name
Test status
Simulation time 7362543076 ps
CPU time 198.76 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:30:26 PM PDT 24
Peak memory 409440 kb
Host smart-9594b38d-460c-4033-9f12-e123b31ccab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108754178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1108754178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.3564370986
Short name T257
Test name
Test status
Simulation time 3679705176 ps
CPU time 4.86 seconds
Started Aug 12 06:27:09 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 217960 kb
Host smart-28e0a6ac-667b-423f-a379-dad01ff3bb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564370986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3564370986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.2619965823
Short name T459
Test name
Test status
Simulation time 168077174 ps
CPU time 1.43 seconds
Started Aug 12 06:27:10 PM PDT 24
Finished Aug 12 06:27:12 PM PDT 24
Peak memory 218976 kb
Host smart-12ec36f8-45b0-42ea-a0d6-b94df6869d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619965823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2619965823 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1136081892
Short name T561
Test name
Test status
Simulation time 3366826502 ps
CPU time 29.88 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:27:37 PM PDT 24
Peak memory 253796 kb
Host smart-542ec313-0d20-4571-b5d1-b496f05537f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136081892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1136081892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2513097529
Short name T311
Test name
Test status
Simulation time 14441112164 ps
CPU time 462.17 seconds
Started Aug 12 06:27:11 PM PDT 24
Finished Aug 12 06:34:58 PM PDT 24
Peak memory 614848 kb
Host smart-16cf656a-7bef-4d79-b789-c60734a0395c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513097529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2513097529 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2054031255
Short name T563
Test name
Test status
Simulation time 1844800961 ps
CPU time 40.64 seconds
Started Aug 12 06:27:13 PM PDT 24
Finished Aug 12 06:27:54 PM PDT 24
Peak memory 217968 kb
Host smart-b8069c02-4729-4163-8959-3bea167adf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054031255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2054031255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.385245623
Short name T351
Test name
Test status
Simulation time 109052349921 ps
CPU time 832.71 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:41:05 PM PDT 24
Peak memory 474756 kb
Host smart-a1e47ec6-fcb2-45cd-8799-bfdb02d55aab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=385245623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.385245623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2437379541
Short name T595
Test name
Test status
Simulation time 36179709 ps
CPU time 0.77 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:27:17 PM PDT 24
Peak memory 205088 kb
Host smart-5c936626-1ee6-494f-8853-e5337317220c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437379541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2437379541 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.3132743120
Short name T431
Test name
Test status
Simulation time 7320242245 ps
CPU time 80.44 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:28:26 PM PDT 24
Peak memory 285072 kb
Host smart-5f066e38-c3af-4e5e-afd6-6c80f513789c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132743120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3132743120 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.1074937314
Short name T254
Test name
Test status
Simulation time 5547974815 ps
CPU time 272.01 seconds
Started Aug 12 06:27:06 PM PDT 24
Finished Aug 12 06:31:38 PM PDT 24
Peak memory 229352 kb
Host smart-92d832bd-4124-4334-8ca5-ea1c96605625
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074937314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.107493731
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.1271009711
Short name T478
Test name
Test status
Simulation time 15618435598 ps
CPU time 270.55 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:31:47 PM PDT 24
Peak memory 328828 kb
Host smart-83f76835-3920-4751-a8a3-22f8e6ba5647
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271009711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1
271009711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.1670597034
Short name T406
Test name
Test status
Simulation time 11845842584 ps
CPU time 374.91 seconds
Started Aug 12 06:27:05 PM PDT 24
Finished Aug 12 06:33:21 PM PDT 24
Peak memory 548080 kb
Host smart-7cfe6f43-927a-4385-92eb-b105f35665d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670597034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1670597034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.35665649
Short name T594
Test name
Test status
Simulation time 873236884 ps
CPU time 2.86 seconds
Started Aug 12 06:27:13 PM PDT 24
Finished Aug 12 06:27:16 PM PDT 24
Peak memory 217664 kb
Host smart-6958756c-d342-4203-9b0b-ac2b3d89aa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35665649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.35665649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3041694940
Short name T539
Test name
Test status
Simulation time 65687297 ps
CPU time 1.28 seconds
Started Aug 12 06:27:20 PM PDT 24
Finished Aug 12 06:27:22 PM PDT 24
Peak memory 218556 kb
Host smart-c3f55d77-9f70-4ff9-b7d7-b1c5e768470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041694940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3041694940 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.3809690483
Short name T84
Test name
Test status
Simulation time 277469046256 ps
CPU time 3413.42 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 07:24:06 PM PDT 24
Peak memory 2930020 kb
Host smart-c20b8ecf-c21f-4fd3-aae9-a97f2f1a604f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809690483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.3809690483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2621123106
Short name T339
Test name
Test status
Simulation time 70969892443 ps
CPU time 400.28 seconds
Started Aug 12 06:27:14 PM PDT 24
Finished Aug 12 06:33:54 PM PDT 24
Peak memory 545716 kb
Host smart-092fa206-7dac-4434-9ebc-00edbada1244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621123106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2621123106 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3484215541
Short name T558
Test name
Test status
Simulation time 557904387 ps
CPU time 29.64 seconds
Started Aug 12 06:27:10 PM PDT 24
Finished Aug 12 06:27:40 PM PDT 24
Peak memory 217852 kb
Host smart-4fe254a1-577c-4d5b-b2bc-4d1217f45389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484215541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3484215541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3637566353
Short name T687
Test name
Test status
Simulation time 260905381799 ps
CPU time 1387.18 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:50:23 PM PDT 24
Peak memory 1414864 kb
Host smart-7f71d27d-ed89-4881-8f95-f0ec48b47e19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3637566353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3637566353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_alert_test.4140948695
Short name T201
Test name
Test status
Simulation time 107059083 ps
CPU time 0.82 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:27:17 PM PDT 24
Peak memory 205052 kb
Host smart-ef36b108-f743-44fe-a9d7-3677dedb5a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140948695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.4140948695 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.1453461815
Short name T270
Test name
Test status
Simulation time 19214913751 ps
CPU time 98.01 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:28:50 PM PDT 24
Peak memory 296748 kb
Host smart-de13af14-0f3c-4245-a3d9-5a5e978ea462
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453461815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1453461815 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1433938513
Short name T631
Test name
Test status
Simulation time 57824162953 ps
CPU time 597.03 seconds
Started Aug 12 06:27:14 PM PDT 24
Finished Aug 12 06:37:11 PM PDT 24
Peak memory 243088 kb
Host smart-77844a72-6f0b-4522-88b7-97258ca19822
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433938513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.143393851
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.2917341082
Short name T215
Test name
Test status
Simulation time 30551042539 ps
CPU time 79.68 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:28:35 PM PDT 24
Peak memory 251116 kb
Host smart-b0952187-eabf-4cfe-9fc2-3e6bdbcd6d6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917341082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.2
917341082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.3625863188
Short name T641
Test name
Test status
Simulation time 56752107954 ps
CPU time 262.32 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:31:37 PM PDT 24
Peak memory 447252 kb
Host smart-ac061f5f-227b-40d9-bf9c-ca0bd3425048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625863188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3625863188 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.1335444048
Short name T392
Test name
Test status
Simulation time 58016902 ps
CPU time 1.25 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:27:17 PM PDT 24
Peak memory 217188 kb
Host smart-64f1bd90-6ce0-43e8-a043-596828440f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335444048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1335444048 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.309498260
Short name T364
Test name
Test status
Simulation time 315031780406 ps
CPU time 5078.25 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 07:51:54 PM PDT 24
Peak memory 3865736 kb
Host smart-548763c8-9847-4476-8a23-c0d3fd39d841
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309498260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an
d_output.309498260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.767790013
Short name T169
Test name
Test status
Simulation time 67002098147 ps
CPU time 487.78 seconds
Started Aug 12 06:27:14 PM PDT 24
Finished Aug 12 06:35:22 PM PDT 24
Peak memory 617120 kb
Host smart-0f52e4af-4274-4559-bab5-76deffab72fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767790013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.767790013 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.448295226
Short name T211
Test name
Test status
Simulation time 2708542683 ps
CPU time 52.2 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:28:07 PM PDT 24
Peak memory 223860 kb
Host smart-f25e5c82-239c-44b6-973a-71f14918adaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448295226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.448295226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.1536453468
Short name T80
Test name
Test status
Simulation time 4688332222 ps
CPU time 354.69 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:33:07 PM PDT 24
Peak memory 294588 kb
Host smart-f197a007-23ab-48cf-9d86-b23c5f20fe5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1536453468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1536453468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_alert_test.52569080
Short name T564
Test name
Test status
Simulation time 40253084 ps
CPU time 0.84 seconds
Started Aug 12 06:27:14 PM PDT 24
Finished Aug 12 06:27:15 PM PDT 24
Peak memory 205056 kb
Host smart-eda9a704-c6d8-4ecd-94f8-e876f08bf868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52569080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.52569080 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.3493598782
Short name T234
Test name
Test status
Simulation time 12171840217 ps
CPU time 357.22 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:33:13 PM PDT 24
Peak memory 519440 kb
Host smart-7bb81514-c1d0-48e7-9fdc-97b3a60860c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493598782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3493598782 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.903928901
Short name T386
Test name
Test status
Simulation time 3205579973 ps
CPU time 93.71 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:28:46 PM PDT 24
Peak memory 224732 kb
Host smart-01c559c3-7f75-4426-8723-08264ea55b42
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903928901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.903928901
+enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.395642314
Short name T495
Test name
Test status
Simulation time 18527711011 ps
CPU time 67.3 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:28:20 PM PDT 24
Peak memory 270520 kb
Host smart-a351a0df-eb1a-4230-9cb6-c5352ec67c47
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395642314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.39
5642314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.3535651361
Short name T220
Test name
Test status
Simulation time 1729298749 ps
CPU time 8.55 seconds
Started Aug 12 06:27:23 PM PDT 24
Finished Aug 12 06:27:32 PM PDT 24
Peak memory 235836 kb
Host smart-adc80f38-856d-48ab-8e51-ce84bf0c02da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535651361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3535651361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.3222376962
Short name T569
Test name
Test status
Simulation time 997382257 ps
CPU time 5.28 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:27:20 PM PDT 24
Peak memory 217536 kb
Host smart-b5cb0b62-ad40-4fcc-a4ed-a385e712b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222376962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3222376962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.411831126
Short name T432
Test name
Test status
Simulation time 31230701 ps
CPU time 1.2 seconds
Started Aug 12 06:27:20 PM PDT 24
Finished Aug 12 06:27:21 PM PDT 24
Peak memory 223716 kb
Host smart-0d2cbf3e-801b-4ecd-adfd-7312c51a40c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411831126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.411831126 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_sideload.3117976177
Short name T370
Test name
Test status
Simulation time 4455536625 ps
CPU time 351.36 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:33:07 PM PDT 24
Peak memory 371608 kb
Host smart-91df946e-9c5a-442f-afd1-17ebe56fdbd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117976177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3117976177 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1270001975
Short name T170
Test name
Test status
Simulation time 240954669 ps
CPU time 11.57 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:27:28 PM PDT 24
Peak memory 219160 kb
Host smart-39b6628c-fc8c-4500-87eb-714d39292a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270001975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1270001975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3690184576
Short name T245
Test name
Test status
Simulation time 86850841580 ps
CPU time 772.92 seconds
Started Aug 12 06:27:13 PM PDT 24
Finished Aug 12 06:40:06 PM PDT 24
Peak memory 628900 kb
Host smart-3e4ca71a-4dd3-4d25-a4f4-8daf684bb50c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3690184576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3690184576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_alert_test.2485645923
Short name T469
Test name
Test status
Simulation time 12828630 ps
CPU time 0.75 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:27:20 PM PDT 24
Peak memory 205112 kb
Host smart-aed6cfb0-1f2d-4715-99f5-cd5fb8b6007f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485645923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2485645923 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.288006325
Short name T653
Test name
Test status
Simulation time 7462607795 ps
CPU time 185.07 seconds
Started Aug 12 06:27:17 PM PDT 24
Finished Aug 12 06:30:22 PM PDT 24
Peak memory 403796 kb
Host smart-5636a4b2-f61b-4022-89ac-721144c0e89d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288006325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.288006325 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.1348071736
Short name T356
Test name
Test status
Simulation time 29653472385 ps
CPU time 666.04 seconds
Started Aug 12 06:27:16 PM PDT 24
Finished Aug 12 06:38:23 PM PDT 24
Peak memory 239396 kb
Host smart-86a3a2a9-440c-4c8d-9bce-033c9e3d055f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348071736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.134807173
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.1417541476
Short name T504
Test name
Test status
Simulation time 7340527175 ps
CPU time 62.15 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:28:14 PM PDT 24
Peak memory 244116 kb
Host smart-d956fd88-d962-4681-932d-4f505b3b5cb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417541476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1
417541476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1704727656
Short name T644
Test name
Test status
Simulation time 22613591890 ps
CPU time 501.48 seconds
Started Aug 12 06:27:15 PM PDT 24
Finished Aug 12 06:35:37 PM PDT 24
Peak memory 673244 kb
Host smart-b955bbd8-ec82-41b1-a7a1-a55e95260f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704727656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1704727656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.1737361656
Short name T57
Test name
Test status
Simulation time 6550917717 ps
CPU time 8.73 seconds
Started Aug 12 06:27:11 PM PDT 24
Finished Aug 12 06:27:20 PM PDT 24
Peak memory 217816 kb
Host smart-7c57c77d-7615-4925-b2fd-62c059638bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737361656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1737361656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.13964135
Short name T711
Test name
Test status
Simulation time 86114812 ps
CPU time 1.19 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:27:20 PM PDT 24
Peak memory 218152 kb
Host smart-c0652451-487d-4dcc-97e0-0a3c30eea9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13964135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.13964135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3403379790
Short name T263
Test name
Test status
Simulation time 578867281587 ps
CPU time 5123.18 seconds
Started Aug 12 06:27:13 PM PDT 24
Finished Aug 12 07:52:38 PM PDT 24
Peak memory 3847892 kb
Host smart-73302eb8-0c2e-4741-a627-fe1b9cd03146
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403379790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3403379790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.1141699609
Short name T665
Test name
Test status
Simulation time 9565118892 ps
CPU time 274.58 seconds
Started Aug 12 06:27:18 PM PDT 24
Finished Aug 12 06:31:53 PM PDT 24
Peak memory 471296 kb
Host smart-bae9cac1-6927-4361-b816-a7f8a89442a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141699609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1141699609 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.571296489
Short name T652
Test name
Test status
Simulation time 220303208 ps
CPU time 5.43 seconds
Started Aug 12 06:27:12 PM PDT 24
Finished Aug 12 06:27:18 PM PDT 24
Peak memory 217412 kb
Host smart-ed671680-5380-41e2-8433-ddfefb2eefc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571296489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.571296489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.3468434310
Short name T250
Test name
Test status
Simulation time 42537794257 ps
CPU time 1418.52 seconds
Started Aug 12 06:27:21 PM PDT 24
Finished Aug 12 06:50:59 PM PDT 24
Peak memory 1182920 kb
Host smart-a70f3396-4c96-402b-839c-5077035ba1f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3468434310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3468434310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2430819928
Short name T416
Test name
Test status
Simulation time 19181750 ps
CPU time 0.79 seconds
Started Aug 12 06:27:26 PM PDT 24
Finished Aug 12 06:27:27 PM PDT 24
Peak memory 205104 kb
Host smart-e2c32368-d9fb-48fa-8f79-ab8f53ab9140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430819928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2430819928 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3086396842
Short name T482
Test name
Test status
Simulation time 6102471451 ps
CPU time 252.6 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:31:31 PM PDT 24
Peak memory 318268 kb
Host smart-4b4f09e5-ccbd-4c4b-a389-368c192cd99a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086396842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3086396842 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.3799356581
Short name T224
Test name
Test status
Simulation time 15612949502 ps
CPU time 344.67 seconds
Started Aug 12 06:27:20 PM PDT 24
Finished Aug 12 06:33:04 PM PDT 24
Peak memory 232344 kb
Host smart-48d2b78b-5306-46e6-a8d8-70509bc0ab15
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799356581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.379935658
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.3877385200
Short name T672
Test name
Test status
Simulation time 1202492853 ps
CPU time 21.43 seconds
Started Aug 12 06:27:21 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 232200 kb
Host smart-303d16ce-9897-4a98-a493-fd8daf7aae74
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877385200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3
877385200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.1573238391
Short name T581
Test name
Test status
Simulation time 29107037799 ps
CPU time 92.44 seconds
Started Aug 12 06:27:34 PM PDT 24
Finished Aug 12 06:29:06 PM PDT 24
Peak memory 294228 kb
Host smart-687687ce-a8b0-4594-b896-e32b9550a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573238391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1573238391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.2455281286
Short name T702
Test name
Test status
Simulation time 3369331953 ps
CPU time 7.96 seconds
Started Aug 12 06:27:30 PM PDT 24
Finished Aug 12 06:27:38 PM PDT 24
Peak memory 218988 kb
Host smart-b2e3cfa6-5f47-48c7-880a-a028181ba2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455281286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2455281286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.67375640
Short name T297
Test name
Test status
Simulation time 1191486460 ps
CPU time 14.65 seconds
Started Aug 12 06:27:20 PM PDT 24
Finished Aug 12 06:27:35 PM PDT 24
Peak memory 237632 kb
Host smart-5c09672d-0773-4603-9038-875ed1d54f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67375640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.67375640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.2887245760
Short name T362
Test name
Test status
Simulation time 80431883633 ps
CPU time 1985.75 seconds
Started Aug 12 06:27:24 PM PDT 24
Finished Aug 12 07:00:31 PM PDT 24
Peak memory 1296404 kb
Host smart-363f4285-e048-4881-8aa2-68ea224c1887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887245760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.2887245760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.2331597246
Short name T681
Test name
Test status
Simulation time 2830335304 ps
CPU time 78.13 seconds
Started Aug 12 06:27:30 PM PDT 24
Finished Aug 12 06:28:49 PM PDT 24
Peak memory 292264 kb
Host smart-99dbce78-6b48-46bf-b60f-adc46d81e827
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331597246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2331597246 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.2953703740
Short name T269
Test name
Test status
Simulation time 1281646872 ps
CPU time 23.48 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 218696 kb
Host smart-eb4194c2-11a7-47b1-bfa2-20165b25198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953703740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2953703740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.1243666559
Short name T623
Test name
Test status
Simulation time 39073809332 ps
CPU time 705.88 seconds
Started Aug 12 06:27:22 PM PDT 24
Finished Aug 12 06:39:08 PM PDT 24
Peak memory 539324 kb
Host smart-ceaebb75-8dc6-418d-a900-48d8eb0f8f5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1243666559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1243666559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_alert_test.3148762461
Short name T253
Test name
Test status
Simulation time 19085382 ps
CPU time 0.82 seconds
Started Aug 12 06:27:31 PM PDT 24
Finished Aug 12 06:27:31 PM PDT 24
Peak memory 205104 kb
Host smart-ec0e4316-73d2-467f-a7ad-5741ead39545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148762461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3148762461 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3592404276
Short name T401
Test name
Test status
Simulation time 30391183075 ps
CPU time 387.72 seconds
Started Aug 12 06:27:19 PM PDT 24
Finished Aug 12 06:33:46 PM PDT 24
Peak memory 564036 kb
Host smart-342c0b62-56cc-4a33-afb4-641d98d7b18b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592404276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3592404276 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.3383629991
Short name T639
Test name
Test status
Simulation time 19983317006 ps
CPU time 389.37 seconds
Started Aug 12 06:27:25 PM PDT 24
Finished Aug 12 06:33:55 PM PDT 24
Peak memory 237084 kb
Host smart-59e82f06-8fbe-490d-9f98-3f17c668e244
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383629991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.338362999
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.1155965681
Short name T598
Test name
Test status
Simulation time 26831615707 ps
CPU time 227.99 seconds
Started Aug 12 06:27:20 PM PDT 24
Finished Aug 12 06:31:08 PM PDT 24
Peak memory 309932 kb
Host smart-b60e31eb-bde5-49c7-aaa5-9c1d9739363b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155965681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1
155965681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.480752181
Short name T583
Test name
Test status
Simulation time 15207763240 ps
CPU time 105.92 seconds
Started Aug 12 06:27:25 PM PDT 24
Finished Aug 12 06:29:11 PM PDT 24
Peak memory 322216 kb
Host smart-1c9c2c52-1517-4a8c-837e-e39c1d02a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480752181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.480752181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.476040031
Short name T70
Test name
Test status
Simulation time 4873010637 ps
CPU time 5.82 seconds
Started Aug 12 06:27:26 PM PDT 24
Finished Aug 12 06:27:33 PM PDT 24
Peak memory 219092 kb
Host smart-a86ad324-156a-4121-9f71-110421df94fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476040031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.476040031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.4281482723
Short name T9
Test name
Test status
Simulation time 34353591 ps
CPU time 1.14 seconds
Started Aug 12 06:27:21 PM PDT 24
Finished Aug 12 06:27:23 PM PDT 24
Peak memory 223652 kb
Host smart-d4d14871-15c8-4b44-9153-ae5b6473facc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281482723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4281482723 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_sideload.1226006802
Short name T429
Test name
Test status
Simulation time 2011730130 ps
CPU time 77.12 seconds
Started Aug 12 06:27:21 PM PDT 24
Finished Aug 12 06:28:38 PM PDT 24
Peak memory 248940 kb
Host smart-34303698-2699-496e-bccf-d77167a2159c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226006802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1226006802 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.299669540
Short name T497
Test name
Test status
Simulation time 730352601 ps
CPU time 4.8 seconds
Started Aug 12 06:27:20 PM PDT 24
Finished Aug 12 06:27:25 PM PDT 24
Peak memory 218136 kb
Host smart-16317a96-4bda-42fe-8636-1c537b043c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299669540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.299669540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.3599169970
Short name T300
Test name
Test status
Simulation time 18355542120 ps
CPU time 586.66 seconds
Started Aug 12 06:27:26 PM PDT 24
Finished Aug 12 06:37:13 PM PDT 24
Peak memory 405956 kb
Host smart-c0491b1f-f96b-47e7-98ca-1f2c54b45233
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3599169970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3599169970 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3016397359
Short name T685
Test name
Test status
Simulation time 71350682 ps
CPU time 0.84 seconds
Started Aug 12 06:27:27 PM PDT 24
Finished Aug 12 06:27:28 PM PDT 24
Peak memory 204992 kb
Host smart-890bf80c-3f1a-41c5-833c-7ddc43d06eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016397359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3016397359 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.2575614013
Short name T441
Test name
Test status
Simulation time 5750104940 ps
CPU time 32.73 seconds
Started Aug 12 06:27:27 PM PDT 24
Finished Aug 12 06:28:00 PM PDT 24
Peak memory 245364 kb
Host smart-2990ba05-e513-4463-8c46-d5e0143543a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575614013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2575614013 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.4042190403
Short name T301
Test name
Test status
Simulation time 32361835847 ps
CPU time 1061.56 seconds
Started Aug 12 06:27:33 PM PDT 24
Finished Aug 12 06:45:15 PM PDT 24
Peak memory 260304 kb
Host smart-c55d5616-dbe5-4c8b-bfc3-4408294cd921
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042190403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.404219040
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.939100364
Short name T493
Test name
Test status
Simulation time 11566646943 ps
CPU time 219.55 seconds
Started Aug 12 06:27:30 PM PDT 24
Finished Aug 12 06:31:10 PM PDT 24
Peak memory 408904 kb
Host smart-2c4c16e8-ef0f-43e3-9568-e088b5891cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939100364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.93
9100364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3786038860
Short name T588
Test name
Test status
Simulation time 9640713090 ps
CPU time 51.68 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:28:30 PM PDT 24
Peak memory 281288 kb
Host smart-5528a81b-f1de-4853-9c33-5c397575bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786038860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3786038860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.3661213829
Short name T231
Test name
Test status
Simulation time 2771265042 ps
CPU time 5.97 seconds
Started Aug 12 06:27:34 PM PDT 24
Finished Aug 12 06:27:40 PM PDT 24
Peak memory 217456 kb
Host smart-1c570840-057c-44a7-b844-77644942c042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661213829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3661213829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.1007519047
Short name T32
Test name
Test status
Simulation time 44475755 ps
CPU time 1.31 seconds
Started Aug 12 06:27:28 PM PDT 24
Finished Aug 12 06:27:30 PM PDT 24
Peak memory 218968 kb
Host smart-c63826c8-b127-47f5-a245-82d57704f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007519047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1007519047 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3146104745
Short name T239
Test name
Test status
Simulation time 61573857222 ps
CPU time 1288.34 seconds
Started Aug 12 06:27:22 PM PDT 24
Finished Aug 12 06:48:51 PM PDT 24
Peak memory 1614644 kb
Host smart-d86bf869-e679-43c8-a3ee-128c8ffc054f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146104745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3146104745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.1388816222
Short name T178
Test name
Test status
Simulation time 8716217890 ps
CPU time 244.8 seconds
Started Aug 12 06:27:25 PM PDT 24
Finished Aug 12 06:31:30 PM PDT 24
Peak memory 458432 kb
Host smart-09d4057b-6579-43a6-a8e3-3dfa76d6de09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388816222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1388816222 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.306176291
Short name T317
Test name
Test status
Simulation time 331973283 ps
CPU time 9.36 seconds
Started Aug 12 06:27:21 PM PDT 24
Finished Aug 12 06:27:31 PM PDT 24
Peak memory 217576 kb
Host smart-42bffce7-d4f0-4162-8c87-a79d27baa2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306176291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.306176291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_alert_test.1935314886
Short name T473
Test name
Test status
Simulation time 13144951 ps
CPU time 0.78 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:32 PM PDT 24
Peak memory 205092 kb
Host smart-f4cb8423-82a6-40c7-8084-3c4fb6b6389f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935314886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1935314886 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.334524177
Short name T374
Test name
Test status
Simulation time 201140060 ps
CPU time 5.56 seconds
Started Aug 12 06:26:38 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 222404 kb
Host smart-8ea5efd5-8661-4a57-88ae-c77719c5ee23
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334524177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.334524177 +enable_masking=0
+sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.1437850937
Short name T166
Test name
Test status
Simulation time 23184200277 ps
CPU time 221.9 seconds
Started Aug 12 06:26:39 PM PDT 24
Finished Aug 12 06:30:21 PM PDT 24
Peak memory 398508 kb
Host smart-be182053-aa90-426f-ac79-da77069abf68
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437850937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.1437850937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.465286258
Short name T619
Test name
Test status
Simulation time 47295137571 ps
CPU time 979.44 seconds
Started Aug 12 06:26:26 PM PDT 24
Finished Aug 12 06:42:45 PM PDT 24
Peak memory 257952 kb
Host smart-18ecf7ba-c596-4268-b794-dd3eaaf61ed4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465286258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.465286258 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3104972706
Short name T354
Test name
Test status
Simulation time 6549104550 ps
CPU time 22.49 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:53 PM PDT 24
Peak memory 226676 kb
Host smart-e31748ee-cb03-4dad-a825-c9a55ceb9ac1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104972706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3104972706 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.4147329909
Short name T197
Test name
Test status
Simulation time 94441416 ps
CPU time 6.01 seconds
Started Aug 12 06:26:32 PM PDT 24
Finished Aug 12 06:26:38 PM PDT 24
Peak memory 217952 kb
Host smart-74da45f9-ad07-4cda-aec9-de0a5c5164bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4147329909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4147329909 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.2950602980
Short name T229
Test name
Test status
Simulation time 5718484870 ps
CPU time 18.88 seconds
Started Aug 12 06:26:24 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 218448 kb
Host smart-b8b48aa7-4473-4a8a-96b8-8c62190afc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950602980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2950602980 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.1751560646
Short name T391
Test name
Test status
Simulation time 22655427202 ps
CPU time 134.11 seconds
Started Aug 12 06:26:36 PM PDT 24
Finished Aug 12 06:28:50 PM PDT 24
Peak memory 319192 kb
Host smart-cdc6e9dc-99d8-4b25-acf3-37997ff41ea4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751560646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.17
51560646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.2911506583
Short name T589
Test name
Test status
Simulation time 3105532188 ps
CPU time 20.68 seconds
Started Aug 12 06:26:35 PM PDT 24
Finished Aug 12 06:26:56 PM PDT 24
Peak memory 240352 kb
Host smart-3331b1b9-6a07-485c-a353-6ef0a3ff8a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911506583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2911506583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.251013643
Short name T600
Test name
Test status
Simulation time 317882437 ps
CPU time 2.17 seconds
Started Aug 12 06:26:32 PM PDT 24
Finished Aug 12 06:26:34 PM PDT 24
Peak memory 218468 kb
Host smart-fa2a0653-0107-4601-83ca-74a1ebc1613b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251013643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.251013643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.2122438613
Short name T86
Test name
Test status
Simulation time 167262595 ps
CPU time 1.59 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 218968 kb
Host smart-57ddc2d3-2203-4eeb-8e48-22b25fabb52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122438613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2122438613 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.1625345228
Short name T698
Test name
Test status
Simulation time 26001076626 ps
CPU time 787.88 seconds
Started Aug 12 06:26:22 PM PDT 24
Finished Aug 12 06:39:30 PM PDT 24
Peak memory 1200468 kb
Host smart-e0e3081a-09b9-4f05-a07c-5ba24862cf8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625345228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.1625345228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.1033868405
Short name T77
Test name
Test status
Simulation time 9131737026 ps
CPU time 312 seconds
Started Aug 12 06:26:27 PM PDT 24
Finished Aug 12 06:31:39 PM PDT 24
Peak memory 352832 kb
Host smart-1b61f6a1-4bd8-48ab-a258-ac159da36c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033868405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1033868405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.3178965550
Short name T62
Test name
Test status
Simulation time 9770209397 ps
CPU time 69.29 seconds
Started Aug 12 06:26:26 PM PDT 24
Finished Aug 12 06:27:36 PM PDT 24
Peak memory 257084 kb
Host smart-7d4acd65-8515-4287-8eaf-8715850bc288
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178965550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3178965550 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.4005158124
Short name T489
Test name
Test status
Simulation time 762088665 ps
CPU time 62.89 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:27:40 PM PDT 24
Peak memory 247584 kb
Host smart-8024bf9f-e02b-4897-b2ec-d58185a89b07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005158124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.4005158124 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3198414225
Short name T553
Test name
Test status
Simulation time 1013412529 ps
CPU time 20.91 seconds
Started Aug 12 06:26:22 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 222324 kb
Host smart-211a8b30-1462-4377-9d26-9177dac32381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198414225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3198414225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.1071376044
Short name T579
Test name
Test status
Simulation time 41429778427 ps
CPU time 165.28 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:29:27 PM PDT 24
Peak memory 310268 kb
Host smart-20dc294f-bd37-4a07-9c3a-3c7d65e1484b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1071376044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1071376044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.926463068
Short name T185
Test name
Test status
Simulation time 76457413 ps
CPU time 2.6 seconds
Started Aug 12 06:26:34 PM PDT 24
Finished Aug 12 06:26:37 PM PDT 24
Peak memory 217924 kb
Host smart-e15bf9c9-935f-420f-aa7f-489ee5ab1071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926463068 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.kmac_test_vectors_kmac.926463068 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.589648578
Short name T172
Test name
Test status
Simulation time 108408729 ps
CPU time 1.99 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 218104 kb
Host smart-3d811d3b-96a9-49b5-8ad1-fa77b226a7f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589648578 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.kmac_test_vectors_kmac_xof.589648578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2895462562
Short name T218
Test name
Test status
Simulation time 1796561420 ps
CPU time 44.5 seconds
Started Aug 12 06:26:27 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 246768 kb
Host smart-5bf4f6ce-a89f-4f59-a121-81f6d3cc147f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2895462562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2895462562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.796373947
Short name T554
Test name
Test status
Simulation time 4883950732 ps
CPU time 44.73 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:27:00 PM PDT 24
Peak memory 243632 kb
Host smart-f5ce5933-b2d1-40ab-9302-e721494b5940
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=796373947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.796373947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.149528899
Short name T272
Test name
Test status
Simulation time 1122978167 ps
CPU time 24.17 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:26:41 PM PDT 24
Peak memory 216976 kb
Host smart-b6713bc8-3f5b-46d3-b9a8-f5ab377c5ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=149528899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.149528899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.59965728
Short name T173
Test name
Test status
Simulation time 9476992868 ps
CPU time 931.43 seconds
Started Aug 12 06:26:24 PM PDT 24
Finished Aug 12 06:41:55 PM PDT 24
Peak memory 712904 kb
Host smart-55f0f3b6-0b82-4960-a67a-94dfc1beb8ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59965728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.59965728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.971091102
Short name T305
Test name
Test status
Simulation time 15116679749 ps
CPU time 184.6 seconds
Started Aug 12 06:26:34 PM PDT 24
Finished Aug 12 06:29:39 PM PDT 24
Peak memory 229564 kb
Host smart-1c30932e-fee7-43d5-b048-2cec2279e6dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=971091102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.971091102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.1652308353
Short name T688
Test name
Test status
Simulation time 88748907622 ps
CPU time 1737.14 seconds
Started Aug 12 06:27:07 PM PDT 24
Finished Aug 12 06:56:04 PM PDT 24
Peak memory 1131900 kb
Host smart-3b5ea820-8d54-4382-aedb-4e88078ee0da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1652308353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1652308353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2947963581
Short name T636
Test name
Test status
Simulation time 23855851 ps
CPU time 0.76 seconds
Started Aug 12 06:27:28 PM PDT 24
Finished Aug 12 06:27:29 PM PDT 24
Peak memory 205024 kb
Host smart-d99bad30-8f2c-49fb-92a4-540b634b4663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947963581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2947963581 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.210735524
Short name T444
Test name
Test status
Simulation time 26041927720 ps
CPU time 115.63 seconds
Started Aug 12 06:27:34 PM PDT 24
Finished Aug 12 06:29:29 PM PDT 24
Peak memory 267008 kb
Host smart-b73f89d7-7373-4d93-95c3-56e95a45447b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210735524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.210735524 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.320175360
Short name T373
Test name
Test status
Simulation time 15738831697 ps
CPU time 481.33 seconds
Started Aug 12 06:27:30 PM PDT 24
Finished Aug 12 06:35:31 PM PDT 24
Peak memory 243508 kb
Host smart-11516719-84df-49c7-95d5-6c545d6860b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320175360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.320175360
+enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1301289746
Short name T199
Test name
Test status
Simulation time 9455592993 ps
CPU time 87.09 seconds
Started Aug 12 06:27:32 PM PDT 24
Finished Aug 12 06:28:59 PM PDT 24
Peak memory 291736 kb
Host smart-41a340dd-afe3-496d-9fef-b843ca24bf10
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301289746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1
301289746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.4094718016
Short name T308
Test name
Test status
Simulation time 5035972315 ps
CPU time 93.18 seconds
Started Aug 12 06:27:28 PM PDT 24
Finished Aug 12 06:29:01 PM PDT 24
Peak memory 267844 kb
Host smart-ac32b741-5fac-40e3-adcc-db56dabe1821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094718016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.4094718016 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2310898741
Short name T397
Test name
Test status
Simulation time 851038143 ps
CPU time 4.99 seconds
Started Aug 12 06:27:28 PM PDT 24
Finished Aug 12 06:27:33 PM PDT 24
Peak memory 217456 kb
Host smart-e414cc12-a43d-438c-8519-3573caca769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310898741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2310898741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.535820122
Short name T213
Test name
Test status
Simulation time 181929343 ps
CPU time 1.47 seconds
Started Aug 12 06:27:27 PM PDT 24
Finished Aug 12 06:27:29 PM PDT 24
Peak memory 223704 kb
Host smart-b2f99d93-1653-46ce-9d7a-072a62a570ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535820122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.535820122 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.610284540
Short name T174
Test name
Test status
Simulation time 202489305677 ps
CPU time 1936.31 seconds
Started Aug 12 06:27:27 PM PDT 24
Finished Aug 12 06:59:44 PM PDT 24
Peak memory 2141636 kb
Host smart-18202d90-7f50-48ee-8666-c2ac3247cf56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610284540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an
d_output.610284540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.1173831402
Short name T382
Test name
Test status
Simulation time 14500295193 ps
CPU time 96.97 seconds
Started Aug 12 06:27:30 PM PDT 24
Finished Aug 12 06:29:07 PM PDT 24
Peak memory 309936 kb
Host smart-5b25d758-c47b-4f72-8a4f-f0e84a29f0b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173831402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1173831402 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.979264822
Short name T635
Test name
Test status
Simulation time 640221951 ps
CPU time 9.09 seconds
Started Aug 12 06:27:27 PM PDT 24
Finished Aug 12 06:27:37 PM PDT 24
Peak memory 218036 kb
Host smart-59b63750-95ef-480d-9958-d0e6e8cedfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979264822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.979264822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.986911882
Short name T81
Test name
Test status
Simulation time 36708588211 ps
CPU time 1176.94 seconds
Started Aug 12 06:27:33 PM PDT 24
Finished Aug 12 06:47:10 PM PDT 24
Peak memory 1026852 kb
Host smart-1b297320-7958-4e94-8d33-73827d7a7847
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=986911882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.986911882 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_alert_test.698558777
Short name T295
Test name
Test status
Simulation time 15217627 ps
CPU time 0.79 seconds
Started Aug 12 06:27:30 PM PDT 24
Finished Aug 12 06:27:31 PM PDT 24
Peak memory 205056 kb
Host smart-237a7587-1e30-437c-8e0f-1b7312492139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698558777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.698558777 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.722960974
Short name T127
Test name
Test status
Simulation time 26303408820 ps
CPU time 227.96 seconds
Started Aug 12 06:27:29 PM PDT 24
Finished Aug 12 06:31:17 PM PDT 24
Peak memory 307740 kb
Host smart-129afea5-8faf-4ef0-b646-7812a155434a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722960974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.722960974 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.3993091441
Short name T570
Test name
Test status
Simulation time 10940857025 ps
CPU time 244.95 seconds
Started Aug 12 06:27:33 PM PDT 24
Finished Aug 12 06:31:38 PM PDT 24
Peak memory 229208 kb
Host smart-c97915e8-7a95-4a64-b1df-854874dd3dc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993091441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.399309144
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.1932403686
Short name T235
Test name
Test status
Simulation time 9531959362 ps
CPU time 59.58 seconds
Started Aug 12 06:27:35 PM PDT 24
Finished Aug 12 06:28:35 PM PDT 24
Peak memory 238608 kb
Host smart-faeae8cb-df5a-47c3-9e69-8a9f5477c47b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932403686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1
932403686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_key_error.1539772496
Short name T603
Test name
Test status
Simulation time 5708707200 ps
CPU time 7.71 seconds
Started Aug 12 06:27:29 PM PDT 24
Finished Aug 12 06:27:37 PM PDT 24
Peak memory 217776 kb
Host smart-97cf1f61-f7ff-40f7-a966-bd1964b50caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539772496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1539772496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.4107773014
Short name T390
Test name
Test status
Simulation time 2053815420 ps
CPU time 51.78 seconds
Started Aug 12 06:27:34 PM PDT 24
Finished Aug 12 06:28:26 PM PDT 24
Peak memory 247688 kb
Host smart-bb4b72cb-885f-4185-867a-0b1be6440eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107773014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.4107773014 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.2944186262
Short name T181
Test name
Test status
Simulation time 32239374582 ps
CPU time 512.88 seconds
Started Aug 12 06:27:35 PM PDT 24
Finished Aug 12 06:36:08 PM PDT 24
Peak memory 556772 kb
Host smart-69b343ea-2c14-4804-91d5-777a9812bb7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944186262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.2944186262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.3395280826
Short name T576
Test name
Test status
Simulation time 3832904961 ps
CPU time 330.26 seconds
Started Aug 12 06:27:29 PM PDT 24
Finished Aug 12 06:32:59 PM PDT 24
Peak memory 354540 kb
Host smart-0df14a3d-ff96-4fdd-b091-9e31ae8d6b04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395280826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3395280826 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.2693162177
Short name T592
Test name
Test status
Simulation time 3346253887 ps
CPU time 49.75 seconds
Started Aug 12 06:27:34 PM PDT 24
Finished Aug 12 06:28:24 PM PDT 24
Peak memory 218940 kb
Host smart-ec3d3deb-7081-4bed-b730-af4d28db9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693162177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2693162177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.3953826878
Short name T79
Test name
Test status
Simulation time 93686051720 ps
CPU time 1294.6 seconds
Started Aug 12 06:27:29 PM PDT 24
Finished Aug 12 06:49:04 PM PDT 24
Peak memory 1037664 kb
Host smart-5342587d-02ed-406d-b90a-b93cecf6b686
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3953826878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3953826878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_alert_test.874571273
Short name T414
Test name
Test status
Simulation time 26571225 ps
CPU time 0.75 seconds
Started Aug 12 06:27:35 PM PDT 24
Finished Aug 12 06:27:36 PM PDT 24
Peak memory 205084 kb
Host smart-42f2bedb-447f-4a97-9096-3d6f4aa17307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874571273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.874571273 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.224005413
Short name T460
Test name
Test status
Simulation time 1318035110 ps
CPU time 55.53 seconds
Started Aug 12 06:27:39 PM PDT 24
Finished Aug 12 06:28:35 PM PDT 24
Peak memory 242332 kb
Host smart-dce819bd-1bb1-4d2d-b8f6-e8dff4b11ed1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224005413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.224005413 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1392486686
Short name T38
Test name
Test status
Simulation time 11430231053 ps
CPU time 256.41 seconds
Started Aug 12 06:27:29 PM PDT 24
Finished Aug 12 06:31:46 PM PDT 24
Peak memory 228260 kb
Host smart-6dd7df38-0228-42af-ba8e-2a01e465883b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392486686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.139248668
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2561917920
Short name T617
Test name
Test status
Simulation time 9972717695 ps
CPU time 78.88 seconds
Started Aug 12 06:27:37 PM PDT 24
Finished Aug 12 06:28:56 PM PDT 24
Peak memory 249384 kb
Host smart-0fa7b84d-ac38-4453-bdbe-9550f7426d61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561917920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2
561917920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3643620086
Short name T654
Test name
Test status
Simulation time 18342401581 ps
CPU time 438.99 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:34:57 PM PDT 24
Peak memory 608572 kb
Host smart-e080efa4-1198-4ac1-af58-c9d683ea874b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643620086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3643620086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.96574379
Short name T633
Test name
Test status
Simulation time 748871392 ps
CPU time 5.33 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:27:44 PM PDT 24
Peak memory 217772 kb
Host smart-a1fd8c1d-e728-4f08-b98b-43be88ec8955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96574379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.96574379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2668507727
Short name T707
Test name
Test status
Simulation time 47952659 ps
CPU time 1.5 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:27:40 PM PDT 24
Peak memory 223444 kb
Host smart-baba14f5-90f3-407b-8028-cc3c2982e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668507727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2668507727 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.3551080335
Short name T513
Test name
Test status
Simulation time 294224462094 ps
CPU time 1238.99 seconds
Started Aug 12 06:27:35 PM PDT 24
Finished Aug 12 06:48:15 PM PDT 24
Peak memory 1602764 kb
Host smart-b55636a2-bba8-4c2e-9c4b-fefe248119f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551080335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.3551080335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_smoke.949264736
Short name T415
Test name
Test status
Simulation time 2591375475 ps
CPU time 36.03 seconds
Started Aug 12 06:27:28 PM PDT 24
Finished Aug 12 06:28:04 PM PDT 24
Peak memory 218236 kb
Host smart-4dd26b3c-d1e8-40f3-bc7c-3b89c917b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949264736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.949264736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.1401021188
Short name T443
Test name
Test status
Simulation time 190907408222 ps
CPU time 2651.54 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 07:11:50 PM PDT 24
Peak memory 1623828 kb
Host smart-8240b646-b7d2-4c0b-b322-0fa03ce7c014
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1401021188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1401021188 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_alert_test.2182627652
Short name T422
Test name
Test status
Simulation time 36259734 ps
CPU time 0.74 seconds
Started Aug 12 06:27:35 PM PDT 24
Finished Aug 12 06:27:36 PM PDT 24
Peak memory 205108 kb
Host smart-67de19be-64e5-4bfe-9b0e-de58d63838c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182627652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2182627652 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.3093523800
Short name T447
Test name
Test status
Simulation time 11465622935 ps
CPU time 144.02 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:30:15 PM PDT 24
Peak memory 280940 kb
Host smart-76be49f8-d2da-4aad-89e2-132a7e198fdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093523800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3093523800 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.3096640729
Short name T484
Test name
Test status
Simulation time 17001113844 ps
CPU time 262.84 seconds
Started Aug 12 06:27:36 PM PDT 24
Finished Aug 12 06:31:59 PM PDT 24
Peak memory 232724 kb
Host smart-3130473c-5956-4598-9a44-93e62196e807
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096640729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.309664072
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_error.3949016192
Short name T537
Test name
Test status
Simulation time 4223388454 ps
CPU time 301.46 seconds
Started Aug 12 06:27:41 PM PDT 24
Finished Aug 12 06:32:43 PM PDT 24
Peak memory 364672 kb
Host smart-21eaad5f-16dd-4c5b-8fc6-21d1d9c90203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949016192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3949016192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.3872930585
Short name T315
Test name
Test status
Simulation time 6724868980 ps
CPU time 4.4 seconds
Started Aug 12 06:27:35 PM PDT 24
Finished Aug 12 06:27:40 PM PDT 24
Peak memory 217932 kb
Host smart-132a7711-e0d8-4420-9495-9f44cc711d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872930585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3872930585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1521102883
Short name T673
Test name
Test status
Simulation time 204294793 ps
CPU time 1.42 seconds
Started Aug 12 06:27:41 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 218168 kb
Host smart-149ccbef-d70f-4b14-953e-2978ce612c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521102883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1521102883 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1719057649
Short name T501
Test name
Test status
Simulation time 88410205731 ps
CPU time 1712.94 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:56:11 PM PDT 24
Peak memory 1174308 kb
Host smart-86db9805-8b5e-4ec7-a355-98e7b7f729da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719057649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1719057649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.1703512185
Short name T210
Test name
Test status
Simulation time 119431709 ps
CPU time 4.38 seconds
Started Aug 12 06:27:36 PM PDT 24
Finished Aug 12 06:27:41 PM PDT 24
Peak memory 217400 kb
Host smart-6fe63409-7f02-4f7d-9036-03d33074a922
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703512185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1703512185 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.1870801080
Short name T409
Test name
Test status
Simulation time 1784957466 ps
CPU time 16.38 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:28:07 PM PDT 24
Peak memory 217956 kb
Host smart-83ce9222-e346-4089-b602-77179857695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870801080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1870801080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3637060289
Short name T679
Test name
Test status
Simulation time 32880761992 ps
CPU time 793.83 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:40:52 PM PDT 24
Peak memory 397268 kb
Host smart-dba8c514-522a-42d4-b35c-e0454d08f3a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3637060289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3637060289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_alert_test.1538940352
Short name T352
Test name
Test status
Simulation time 57275241 ps
CPU time 0.8 seconds
Started Aug 12 06:27:36 PM PDT 24
Finished Aug 12 06:27:37 PM PDT 24
Peak memory 205040 kb
Host smart-e908f142-f259-438b-8504-651ce558ba2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538940352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1538940352 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.519359683
Short name T467
Test name
Test status
Simulation time 4967478073 ps
CPU time 26.35 seconds
Started Aug 12 06:27:41 PM PDT 24
Finished Aug 12 06:28:07 PM PDT 24
Peak memory 241820 kb
Host smart-85251842-2ff5-4770-ab35-ecbfc5b2c740
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519359683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.519359683 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.2807444899
Short name T643
Test name
Test status
Simulation time 58651975262 ps
CPU time 587.67 seconds
Started Aug 12 06:27:37 PM PDT 24
Finished Aug 12 06:37:25 PM PDT 24
Peak memory 245444 kb
Host smart-6b47b96b-ba7e-4e55-b2a3-22ad50f2ba91
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807444899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.280744489
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.1184226890
Short name T571
Test name
Test status
Simulation time 15455971424 ps
CPU time 274.27 seconds
Started Aug 12 06:27:37 PM PDT 24
Finished Aug 12 06:32:11 PM PDT 24
Peak memory 460112 kb
Host smart-afb64147-dc31-4635-b9ef-312f36728f4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184226890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1
184226890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.3295429999
Short name T340
Test name
Test status
Simulation time 15572649923 ps
CPU time 63.81 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:28:42 PM PDT 24
Peak memory 287340 kb
Host smart-ca8e2726-fe5a-48d7-80db-10e73f9454b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295429999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3295429999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.2045899946
Short name T58
Test name
Test status
Simulation time 6694673519 ps
CPU time 7.48 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:27:59 PM PDT 24
Peak memory 217964 kb
Host smart-9add849a-32d8-4add-a9a1-74716f650e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045899946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2045899946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2335235107
Short name T411
Test name
Test status
Simulation time 73802655 ps
CPU time 1.27 seconds
Started Aug 12 06:27:35 PM PDT 24
Finished Aug 12 06:27:36 PM PDT 24
Peak memory 219136 kb
Host smart-77432033-0860-464c-a4f0-78df8704bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335235107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2335235107 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.1760538709
Short name T366
Test name
Test status
Simulation time 51442819582 ps
CPU time 2348.46 seconds
Started Aug 12 06:27:41 PM PDT 24
Finished Aug 12 07:06:50 PM PDT 24
Peak memory 2493288 kb
Host smart-29850fe5-381d-4d2e-bb39-3dc71e278968
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760538709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.1760538709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.617037332
Short name T395
Test name
Test status
Simulation time 8928045562 ps
CPU time 186.07 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:30:44 PM PDT 24
Peak memory 307668 kb
Host smart-7ddff03b-583a-463d-9cc4-d4950a9576f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617037332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.617037332 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.1142451312
Short name T477
Test name
Test status
Simulation time 3153362358 ps
CPU time 16.46 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:27:54 PM PDT 24
Peak memory 218272 kb
Host smart-b9a59b8f-edd3-47f4-84f5-fb8e6eff7b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142451312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1142451312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.1174766446
Short name T333
Test name
Test status
Simulation time 34670266528 ps
CPU time 262.5 seconds
Started Aug 12 06:27:38 PM PDT 24
Finished Aug 12 06:32:01 PM PDT 24
Peak memory 289660 kb
Host smart-725cf003-0650-4c41-bcb0-d663ac312afe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1174766446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1174766446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_alert_test.192270968
Short name T461
Test name
Test status
Simulation time 150841854 ps
CPU time 0.87 seconds
Started Aug 12 06:27:45 PM PDT 24
Finished Aug 12 06:27:46 PM PDT 24
Peak memory 205024 kb
Host smart-e569ef19-d107-4b31-a2fe-91534f579923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192270968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.192270968 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.1623690063
Short name T540
Test name
Test status
Simulation time 8550115066 ps
CPU time 198.55 seconds
Started Aug 12 06:27:48 PM PDT 24
Finished Aug 12 06:31:07 PM PDT 24
Peak memory 401596 kb
Host smart-7bb404bf-f9f0-43d5-8e9b-2a3434ba8bf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623690063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1623690063 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.2979190317
Short name T168
Test name
Test status
Simulation time 28289867668 ps
CPU time 445.52 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 06:35:07 PM PDT 24
Peak memory 234184 kb
Host smart-f4796b06-0f28-47bf-b529-6ba1feb52acf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979190317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.297919031
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.2722088998
Short name T500
Test name
Test status
Simulation time 8210604929 ps
CPU time 182.97 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 06:30:45 PM PDT 24
Peak memory 386900 kb
Host smart-7f236980-5616-4204-aca7-f4b87c09cdb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722088998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2
722088998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.2738970534
Short name T369
Test name
Test status
Simulation time 4020481686 ps
CPU time 79.02 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 06:29:01 PM PDT 24
Peak memory 273084 kb
Host smart-c6c14446-940c-419f-9295-f1964c5a7793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738970534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2738970534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.376125990
Short name T714
Test name
Test status
Simulation time 777285725 ps
CPU time 1.18 seconds
Started Aug 12 06:27:44 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 216720 kb
Host smart-fcde1070-db54-4f87-acbe-9429521f2e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376125990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.376125990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.3670407397
Short name T491
Test name
Test status
Simulation time 56069799 ps
CPU time 1.21 seconds
Started Aug 12 06:27:41 PM PDT 24
Finished Aug 12 06:27:42 PM PDT 24
Peak memory 218848 kb
Host smart-885cb58f-93f2-4614-9a36-65cfcd69ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670407397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3670407397 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2304302138
Short name T258
Test name
Test status
Simulation time 158488352982 ps
CPU time 3000.07 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 07:17:42 PM PDT 24
Peak memory 2737908 kb
Host smart-b47eb187-8fbf-4286-a130-a663113fe9df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304302138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2304302138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.1425546709
Short name T695
Test name
Test status
Simulation time 4472515477 ps
CPU time 145.42 seconds
Started Aug 12 06:27:43 PM PDT 24
Finished Aug 12 06:30:08 PM PDT 24
Peak memory 288692 kb
Host smart-b356b52c-9dbf-49af-bd09-8bc648d7aefe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425546709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1425546709 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.453482039
Short name T360
Test name
Test status
Simulation time 1770903978 ps
CPU time 47.97 seconds
Started Aug 12 06:27:52 PM PDT 24
Finished Aug 12 06:28:40 PM PDT 24
Peak memory 218152 kb
Host smart-37c02b08-be99-4752-8663-d43b63920ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453482039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.453482039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.2287914959
Short name T474
Test name
Test status
Simulation time 8006149249 ps
CPU time 145.92 seconds
Started Aug 12 06:27:48 PM PDT 24
Finished Aug 12 06:30:14 PM PDT 24
Peak memory 274048 kb
Host smart-834de3de-a150-4c7f-b57c-c244a5413181
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2287914959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2287914959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_alert_test.3829996424
Short name T324
Test name
Test status
Simulation time 28828431 ps
CPU time 0.78 seconds
Started Aug 12 06:27:40 PM PDT 24
Finished Aug 12 06:27:41 PM PDT 24
Peak memory 205088 kb
Host smart-ad82dd4c-bfa1-41dd-ad0d-694bdad2dc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829996424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3829996424 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3892280836
Short name T551
Test name
Test status
Simulation time 801905741 ps
CPU time 68.74 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 06:28:50 PM PDT 24
Peak memory 223856 kb
Host smart-a7967770-41d0-4fea-a3ef-ed1dff815fa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892280836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.389228083
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.4152511689
Short name T274
Test name
Test status
Simulation time 10894074292 ps
CPU time 211.72 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:31:23 PM PDT 24
Peak memory 393852 kb
Host smart-d3fcf7fd-b2f4-41e0-ac27-a0f107adf8f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152511689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.4
152511689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.1827793532
Short name T30
Test name
Test status
Simulation time 90805416621 ps
CPU time 324.31 seconds
Started Aug 12 06:27:40 PM PDT 24
Finished Aug 12 06:33:05 PM PDT 24
Peak memory 500384 kb
Host smart-981d74f5-4313-466e-aff3-b4ffe1c8f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827793532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1827793532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2499271888
Short name T256
Test name
Test status
Simulation time 458040203 ps
CPU time 1.84 seconds
Started Aug 12 06:27:43 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 217600 kb
Host smart-03e68c0f-63b9-4f46-b711-ed6f4d674c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499271888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2499271888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.338566220
Short name T388
Test name
Test status
Simulation time 42734673 ps
CPU time 1.37 seconds
Started Aug 12 06:27:44 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 217196 kb
Host smart-953d9ce6-6ef2-4eae-8624-aa637ad0cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338566220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.338566220 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2434829563
Short name T541
Test name
Test status
Simulation time 71194003427 ps
CPU time 4052.77 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 07:35:15 PM PDT 24
Peak memory 3359084 kb
Host smart-db4c3d37-cc67-40d7-b78c-2d700c56264d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434829563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2434829563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.3698546396
Short name T607
Test name
Test status
Simulation time 4194600507 ps
CPU time 123.53 seconds
Started Aug 12 06:27:44 PM PDT 24
Finished Aug 12 06:29:47 PM PDT 24
Peak memory 326668 kb
Host smart-8863cf78-3dc1-4dd7-96cb-fc735c6a42e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698546396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3698546396 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.3499574833
Short name T255
Test name
Test status
Simulation time 3620515597 ps
CPU time 48.75 seconds
Started Aug 12 06:27:49 PM PDT 24
Finished Aug 12 06:28:38 PM PDT 24
Peak memory 218184 kb
Host smart-18b33071-e945-4a8f-a743-6a6c42f6ccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499574833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3499574833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.130030099
Short name T475
Test name
Test status
Simulation time 29520939063 ps
CPU time 661.87 seconds
Started Aug 12 06:27:43 PM PDT 24
Finished Aug 12 06:38:45 PM PDT 24
Peak memory 403528 kb
Host smart-cd210b83-ff52-47c3-93a4-4352f71c016f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=130030099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.130030099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1819193573
Short name T609
Test name
Test status
Simulation time 28715069 ps
CPU time 0.8 seconds
Started Aug 12 06:27:49 PM PDT 24
Finished Aug 12 06:27:50 PM PDT 24
Peak memory 205124 kb
Host smart-3ace5f9c-c177-406c-a931-4f470728f1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819193573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1819193573 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.3095425259
Short name T618
Test name
Test status
Simulation time 20760668429 ps
CPU time 294.54 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 06:32:37 PM PDT 24
Peak memory 482944 kb
Host smart-158b0f75-ab26-4dd2-ac15-5e255d967246
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095425259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3095425259 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.3087876664
Short name T543
Test name
Test status
Simulation time 6577245401 ps
CPU time 242.73 seconds
Started Aug 12 06:27:48 PM PDT 24
Finished Aug 12 06:31:51 PM PDT 24
Peak memory 232404 kb
Host smart-831cb59d-3fcd-4d2b-88c4-03958f575774
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087876664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.308787666
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.1034894732
Short name T651
Test name
Test status
Simulation time 76969836375 ps
CPU time 161.82 seconds
Started Aug 12 06:27:48 PM PDT 24
Finished Aug 12 06:30:30 PM PDT 24
Peak memory 363032 kb
Host smart-38257214-a304-4e92-be82-fc741f5010ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034894732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1
034894732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.1024010683
Short name T559
Test name
Test status
Simulation time 7134887128 ps
CPU time 152.53 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:30:24 PM PDT 24
Peak memory 374208 kb
Host smart-cfad69eb-49b5-43c5-837a-092a72f23a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024010683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1024010683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.711327838
Short name T696
Test name
Test status
Simulation time 4287263733 ps
CPU time 6.15 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:27:58 PM PDT 24
Peak memory 218136 kb
Host smart-71c54d1b-2b83-4bad-a9fa-a837e9247e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711327838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.711327838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.2809952182
Short name T5
Test name
Test status
Simulation time 77256134 ps
CPU time 1.77 seconds
Started Aug 12 06:27:44 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 217156 kb
Host smart-edc85384-fe22-4318-a464-545461186a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809952182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2809952182 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.3945723241
Short name T560
Test name
Test status
Simulation time 113608658827 ps
CPU time 3143.54 seconds
Started Aug 12 06:27:49 PM PDT 24
Finished Aug 12 07:20:13 PM PDT 24
Peak memory 2824204 kb
Host smart-e0877f06-a5aa-4a3e-ba0b-afbf35cec6d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945723241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.3945723241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.571402810
Short name T535
Test name
Test status
Simulation time 5617944971 ps
CPU time 143.53 seconds
Started Aug 12 06:27:41 PM PDT 24
Finished Aug 12 06:30:05 PM PDT 24
Peak memory 355368 kb
Host smart-38b7c235-fa39-4e5a-b53c-2d33a0687eba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571402810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.571402810 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3568742766
Short name T177
Test name
Test status
Simulation time 36096769 ps
CPU time 1.92 seconds
Started Aug 12 06:27:42 PM PDT 24
Finished Aug 12 06:27:44 PM PDT 24
Peak memory 218156 kb
Host smart-bb454d91-6fca-4fa4-9791-4fd37d10b89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568742766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3568742766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.2699438520
Short name T232
Test name
Test status
Simulation time 68620192782 ps
CPU time 901.62 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:42:53 PM PDT 24
Peak memory 576952 kb
Host smart-11a21e6c-ddd4-43ad-a03b-be42010e668d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2699438520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2699438520 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3044875899
Short name T45
Test name
Test status
Simulation time 21963775 ps
CPU time 0.79 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:27:52 PM PDT 24
Peak memory 205112 kb
Host smart-4739db44-0ced-47b9-ab33-edd794e60c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044875899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3044875899 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.4083571035
Short name T520
Test name
Test status
Simulation time 12686884516 ps
CPU time 164.31 seconds
Started Aug 12 06:27:49 PM PDT 24
Finished Aug 12 06:30:34 PM PDT 24
Peak memory 284116 kb
Host smart-7e233d0f-52e9-4f3c-bf9f-0614a35e3e9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083571035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.4083571035 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.1395451516
Short name T496
Test name
Test status
Simulation time 63621798425 ps
CPU time 951.78 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:43:43 PM PDT 24
Peak memory 259432 kb
Host smart-82a1b8e8-20f8-40a8-9e45-ed89b15d74d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395451516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.139545151
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.514818203
Short name T519
Test name
Test status
Simulation time 13533560977 ps
CPU time 291.86 seconds
Started Aug 12 06:27:49 PM PDT 24
Finished Aug 12 06:32:41 PM PDT 24
Peak memory 338032 kb
Host smart-ed356a31-f7a9-4d54-a9e0-38306aedf85c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514818203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.51
4818203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.3346515054
Short name T27
Test name
Test status
Simulation time 2211871613 ps
CPU time 155.7 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:30:27 PM PDT 24
Peak memory 297896 kb
Host smart-4948a068-fbbf-450b-a48c-4fa397095ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346515054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3346515054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.2450277925
Short name T442
Test name
Test status
Simulation time 1960551641 ps
CPU time 6.3 seconds
Started Aug 12 06:27:50 PM PDT 24
Finished Aug 12 06:27:56 PM PDT 24
Peak memory 217820 kb
Host smart-0ef1346a-4e01-4795-9794-2f17126c0102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450277925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2450277925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.1737957126
Short name T304
Test name
Test status
Simulation time 110330719 ps
CPU time 1.32 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:27:53 PM PDT 24
Peak memory 218152 kb
Host smart-777e3b62-a704-45e4-bd11-61b207d0fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737957126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1737957126 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.1629930318
Short name T664
Test name
Test status
Simulation time 12238156157 ps
CPU time 368.01 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:33:59 PM PDT 24
Peak memory 457624 kb
Host smart-c60a5970-202d-49c4-9afe-cfa1c601846b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629930318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.1629930318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.1035696237
Short name T327
Test name
Test status
Simulation time 3019133510 ps
CPU time 86.04 seconds
Started Aug 12 06:27:52 PM PDT 24
Finished Aug 12 06:29:19 PM PDT 24
Peak memory 301248 kb
Host smart-0fbd2bd2-8c62-4dcf-b727-6156bcfe4fd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035696237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1035696237 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1080900948
Short name T66
Test name
Test status
Simulation time 979262474 ps
CPU time 20.62 seconds
Started Aug 12 06:27:50 PM PDT 24
Finished Aug 12 06:28:10 PM PDT 24
Peak memory 218608 kb
Host smart-4e399519-c6ef-4bd4-bce4-f426f2aefc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080900948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1080900948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3769631518
Short name T682
Test name
Test status
Simulation time 71794429194 ps
CPU time 417.27 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:34:48 PM PDT 24
Peak memory 517272 kb
Host smart-282a2fd7-c227-4548-bea4-142cf1670f30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3769631518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3769631518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_alert_test.186897126
Short name T285
Test name
Test status
Simulation time 18720465 ps
CPU time 0.79 seconds
Started Aug 12 06:27:50 PM PDT 24
Finished Aug 12 06:27:51 PM PDT 24
Peak memory 204964 kb
Host smart-c4879697-95e2-4018-9827-d32a53d8d561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186897126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.186897126 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3299881063
Short name T380
Test name
Test status
Simulation time 1257655771 ps
CPU time 57.19 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:28:49 PM PDT 24
Peak memory 241780 kb
Host smart-a835d52a-74d9-4acc-bd04-362a67d4f185
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299881063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3299881063 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.1894497476
Short name T506
Test name
Test status
Simulation time 21914773696 ps
CPU time 179.4 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:30:51 PM PDT 24
Peak memory 225036 kb
Host smart-4485250b-bb6e-4820-a0e7-8a8411e56949
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894497476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.189449747
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2486930743
Short name T217
Test name
Test status
Simulation time 68251582467 ps
CPU time 290.36 seconds
Started Aug 12 06:27:50 PM PDT 24
Finished Aug 12 06:32:40 PM PDT 24
Peak memory 456352 kb
Host smart-fd8d9c56-684e-4869-bc17-86f084e66841
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486930743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2
486930743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.273151858
Short name T555
Test name
Test status
Simulation time 3394493681 ps
CPU time 24.83 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:28:16 PM PDT 24
Peak memory 248572 kb
Host smart-8a69db62-5d46-481d-b9fb-ae4ab7cf6bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273151858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.273151858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.754324915
Short name T248
Test name
Test status
Simulation time 1435448209 ps
CPU time 2.84 seconds
Started Aug 12 06:27:53 PM PDT 24
Finished Aug 12 06:27:56 PM PDT 24
Peak memory 218972 kb
Host smart-5669e7c6-cb70-4406-afd7-1293c6eb68c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754324915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.754324915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.2264466941
Short name T568
Test name
Test status
Simulation time 116305463 ps
CPU time 1.32 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:27:53 PM PDT 24
Peak memory 217180 kb
Host smart-ab6165c2-0e3b-4bb6-a9e7-3e8efff8c12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264466941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2264466941 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3655133452
Short name T470
Test name
Test status
Simulation time 21311034504 ps
CPU time 2584.67 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 07:10:56 PM PDT 24
Peak memory 1489820 kb
Host smart-3e15a926-1356-4001-8961-c6b749aee01b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655133452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3655133452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1736684075
Short name T296
Test name
Test status
Simulation time 15307263580 ps
CPU time 203.28 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:31:15 PM PDT 24
Peak memory 413636 kb
Host smart-aac1e601-130a-42ab-aa80-e1642ee26ae5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736684075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1736684075 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1230420762
Short name T586
Test name
Test status
Simulation time 7485986255 ps
CPU time 43.62 seconds
Started Aug 12 06:27:52 PM PDT 24
Finished Aug 12 06:28:36 PM PDT 24
Peak memory 217884 kb
Host smart-9fb2abb7-e852-448c-9f5e-3b619b666f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230420762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1230420762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.3830790030
Short name T634
Test name
Test status
Simulation time 163103155444 ps
CPU time 3986.7 seconds
Started Aug 12 06:27:48 PM PDT 24
Finished Aug 12 07:34:16 PM PDT 24
Peak memory 970536 kb
Host smart-7187a95e-a865-450c-adeb-9d952a4915aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3830790030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3830790030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_alert_test.1577349583
Short name T209
Test name
Test status
Simulation time 95494658 ps
CPU time 0.83 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:26:42 PM PDT 24
Peak memory 205092 kb
Host smart-3072ae21-796b-403d-8b43-e8be8ad4d955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577349583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1577349583 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.2686663922
Short name T291
Test name
Test status
Simulation time 7110416684 ps
CPU time 64.98 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:27:42 PM PDT 24
Peak memory 274664 kb
Host smart-1f0fa93e-21d9-4171-8c41-7432f6cf558e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686663922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2686663922 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.511167305
Short name T384
Test name
Test status
Simulation time 104875644414 ps
CPU time 311.87 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:31:56 PM PDT 24
Peak memory 348536 kb
Host smart-19eefa11-7e42-4652-b4b7-10ab06d4eb9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511167305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_part
ial_data.511167305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.1837999322
Short name T433
Test name
Test status
Simulation time 57279738966 ps
CPU time 970.76 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:42:48 PM PDT 24
Peak memory 260400 kb
Host smart-4945badf-a7c1-44c7-9559-40fe11bd12c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837999322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1837999322
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2292243788
Short name T456
Test name
Test status
Simulation time 708016724 ps
CPU time 18.96 seconds
Started Aug 12 06:26:32 PM PDT 24
Finished Aug 12 06:26:51 PM PDT 24
Peak memory 223604 kb
Host smart-7ab039ba-67ac-4b28-9d48-d2353ff9b768
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2292243788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2292243788 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.1457874459
Short name T240
Test name
Test status
Simulation time 946886044 ps
CPU time 7.52 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:26:51 PM PDT 24
Peak memory 216552 kb
Host smart-0123de5b-4158-4b42-8a6b-f3c7f6f1a377
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1457874459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1457874459 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.2124646590
Short name T43
Test name
Test status
Simulation time 19226192296 ps
CPU time 70.94 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:27:52 PM PDT 24
Peak memory 218796 kb
Host smart-e3b271df-ece5-4592-bd74-9cd89900bfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124646590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2124646590 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.2130586003
Short name T379
Test name
Test status
Simulation time 46224420856 ps
CPU time 247.9 seconds
Started Aug 12 06:26:28 PM PDT 24
Finished Aug 12 06:30:36 PM PDT 24
Peak memory 437560 kb
Host smart-73beaafd-ef71-4637-9c1c-c16b69e526bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130586003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.21
30586003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.56714139
Short name T378
Test name
Test status
Simulation time 19251558923 ps
CPU time 414.33 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:33:35 PM PDT 24
Peak memory 591316 kb
Host smart-89fa1846-97cc-423e-bbcf-bee9afaec1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56714139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.56714139 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.1521475742
Short name T577
Test name
Test status
Simulation time 786227411 ps
CPU time 4.4 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:36 PM PDT 24
Peak memory 217776 kb
Host smart-9f1a827e-d6c3-4083-8a12-6b9f7e8c48a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521475742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1521475742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1666582355
Short name T585
Test name
Test status
Simulation time 37366455 ps
CPU time 1.25 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 218840 kb
Host smart-7152fa7d-5a67-4b54-91cc-59e91799aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666582355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1666582355 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.3289869855
Short name T230
Test name
Test status
Simulation time 286736631004 ps
CPU time 3267.86 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 07:21:15 PM PDT 24
Peak memory 2785880 kb
Host smart-320ae07a-bb0a-4713-baeb-0694c84a796f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289869855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.3289869855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.1316983434
Short name T267
Test name
Test status
Simulation time 1830859796 ps
CPU time 111.87 seconds
Started Aug 12 06:26:38 PM PDT 24
Finished Aug 12 06:28:30 PM PDT 24
Peak memory 267116 kb
Host smart-565a75d8-edce-4267-b496-4bd117c83a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316983434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1316983434 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.164413010
Short name T11
Test name
Test status
Simulation time 1670862577 ps
CPU time 25.9 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:27:07 PM PDT 24
Peak memory 241348 kb
Host smart-f9039971-d03b-4b17-8fbc-5bbecfcc4834
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164413010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.164413010 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.2980737589
Short name T310
Test name
Test status
Simulation time 14360106205 ps
CPU time 447.54 seconds
Started Aug 12 06:26:23 PM PDT 24
Finished Aug 12 06:33:51 PM PDT 24
Peak memory 599040 kb
Host smart-4b9537ab-1634-4225-8599-d20888ce5b6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980737589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2980737589 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.2565044310
Short name T680
Test name
Test status
Simulation time 993995482 ps
CPU time 21.26 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:52 PM PDT 24
Peak memory 218120 kb
Host smart-b65e89c7-e4e0-418e-96c7-20cc1a177f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565044310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2565044310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.2522677936
Short name T75
Test name
Test status
Simulation time 143840982371 ps
CPU time 1355.26 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:49:17 PM PDT 24
Peak memory 1195552 kb
Host smart-8ef3d2f4-0173-4f94-86f5-18ca199ded5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2522677936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2522677936 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.499969784
Short name T670
Test name
Test status
Simulation time 32360135 ps
CPU time 2.1 seconds
Started Aug 12 06:26:33 PM PDT 24
Finished Aug 12 06:26:36 PM PDT 24
Peak memory 218052 kb
Host smart-53d1956c-615d-4fb3-8638-91a86fd1720f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499969784 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.kmac_test_vectors_kmac.499969784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.1612392400
Short name T420
Test name
Test status
Simulation time 340649297 ps
CPU time 2.42 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:26:44 PM PDT 24
Peak memory 217968 kb
Host smart-ebbac027-461c-41c3-8776-c87185df6606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612392400 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1612392400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.1324879504
Short name T601
Test name
Test status
Simulation time 202496600005 ps
CPU time 2964.29 seconds
Started Aug 12 06:26:28 PM PDT 24
Finished Aug 12 07:15:53 PM PDT 24
Peak memory 3118912 kb
Host smart-ed30a3b7-1a22-44ea-b2a7-a47de6703383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1324879504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1324879504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1888821695
Short name T400
Test name
Test status
Simulation time 1678834152 ps
CPU time 39.89 seconds
Started Aug 12 06:26:26 PM PDT 24
Finished Aug 12 06:27:06 PM PDT 24
Peak memory 241996 kb
Host smart-6a1a2d05-f93a-4859-a319-1904be088f1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1888821695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1888821695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2385254339
Short name T394
Test name
Test status
Simulation time 166390725641 ps
CPU time 1872.66 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:57:44 PM PDT 24
Peak memory 2360196 kb
Host smart-01965adb-89d9-4f11-a046-4f7392de348a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2385254339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2385254339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3444614160
Short name T163
Test name
Test status
Simulation time 2901413075 ps
CPU time 18.48 seconds
Started Aug 12 06:26:45 PM PDT 24
Finished Aug 12 06:27:04 PM PDT 24
Peak memory 217116 kb
Host smart-c2cc75d0-a27c-4183-889e-92e7c79a0035
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3444614160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3444614160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3290046063
Short name T226
Test name
Test status
Simulation time 144855065945 ps
CPU time 3570.36 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 07:26:12 PM PDT 24
Peak memory 3612332 kb
Host smart-db7d20ec-ca4f-4562-b47b-9c3e5615cf63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3290046063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3290046063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.4049392549
Short name T615
Test name
Test status
Simulation time 69201085970 ps
CPU time 1779.9 seconds
Started Aug 12 06:26:32 PM PDT 24
Finished Aug 12 06:56:12 PM PDT 24
Peak memory 1113328 kb
Host smart-e86ca539-c136-436e-a1c5-e6d4dfd1b4f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4049392549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.4049392549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.239885572
Short name T483
Test name
Test status
Simulation time 80373746 ps
CPU time 0.88 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:27:58 PM PDT 24
Peak memory 205092 kb
Host smart-2964d15b-193d-483f-9ccc-898c3ef24b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239885572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.239885572 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3463150587
Short name T294
Test name
Test status
Simulation time 6172798205 ps
CPU time 159.65 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:30:31 PM PDT 24
Peak memory 362512 kb
Host smart-149b3e8b-cb73-4013-8a2b-537bebae0c39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463150587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3463150587 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.210742199
Short name T261
Test name
Test status
Simulation time 29869200466 ps
CPU time 232.43 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:31:44 PM PDT 24
Peak memory 228804 kb
Host smart-9c7a3d3c-7fe0-450f-9cab-4f59c23e93d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210742199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.210742199
+enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.4290657944
Short name T562
Test name
Test status
Simulation time 9221188064 ps
CPU time 20.02 seconds
Started Aug 12 06:27:49 PM PDT 24
Finished Aug 12 06:28:09 PM PDT 24
Peak memory 222196 kb
Host smart-a13bc5e7-ccf7-44ca-a227-cbd64546d44e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290657944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.4
290657944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.2994384707
Short name T383
Test name
Test status
Simulation time 4792397486 ps
CPU time 321.85 seconds
Started Aug 12 06:27:52 PM PDT 24
Finished Aug 12 06:33:14 PM PDT 24
Peak memory 366508 kb
Host smart-ee3c656d-226a-4d27-abf1-83b7d4f09b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994384707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2994384707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.3251973849
Short name T275
Test name
Test status
Simulation time 2742383062 ps
CPU time 4.67 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:27:56 PM PDT 24
Peak memory 217860 kb
Host smart-73ee479d-d433-4d2b-83e4-3bf2a2363b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251973849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3251973849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.2854232911
Short name T637
Test name
Test status
Simulation time 74647697 ps
CPU time 1.45 seconds
Started Aug 12 06:27:51 PM PDT 24
Finished Aug 12 06:27:52 PM PDT 24
Peak memory 217800 kb
Host smart-8b9df2f8-797c-4901-a6bc-3bf35de4966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854232911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2854232911 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.3881456527
Short name T280
Test name
Test status
Simulation time 83670019645 ps
CPU time 3221.46 seconds
Started Aug 12 06:27:49 PM PDT 24
Finished Aug 12 07:21:31 PM PDT 24
Peak memory 2958624 kb
Host smart-007a47dc-5cbc-43fb-8021-865c1f216f3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881456527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.3881456527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.594149184
Short name T458
Test name
Test status
Simulation time 1392877650 ps
CPU time 116.07 seconds
Started Aug 12 06:27:50 PM PDT 24
Finished Aug 12 06:29:46 PM PDT 24
Peak memory 268504 kb
Host smart-5ecbcbc4-51b1-4e2e-979b-5abc79248aed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594149184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.594149184 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.2267130590
Short name T449
Test name
Test status
Simulation time 799073259 ps
CPU time 16.6 seconds
Started Aug 12 06:27:50 PM PDT 24
Finished Aug 12 06:28:06 PM PDT 24
Peak memory 221656 kb
Host smart-1e293137-29ed-4bc7-b147-5eb605e6253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267130590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2267130590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.2256987988
Short name T134
Test name
Test status
Simulation time 232802645468 ps
CPU time 1471.04 seconds
Started Aug 12 06:27:56 PM PDT 24
Finished Aug 12 06:52:27 PM PDT 24
Peak memory 982744 kb
Host smart-6bab18a7-bf9a-4ae4-aa3d-1f40bda75731
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2256987988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2256987988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_alert_test.3520742627
Short name T47
Test name
Test status
Simulation time 33147748 ps
CPU time 0.77 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:27:58 PM PDT 24
Peak memory 205084 kb
Host smart-3939d7c6-c698-4bf2-99e9-5d0d4639a711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520742627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3520742627 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.1831414063
Short name T336
Test name
Test status
Simulation time 67340433334 ps
CPU time 249.12 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:32:08 PM PDT 24
Peak memory 410864 kb
Host smart-3f5a81ca-6899-481f-9381-852b0871e6a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831414063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1831414063 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.1000838448
Short name T221
Test name
Test status
Simulation time 17962275316 ps
CPU time 869.54 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:42:29 PM PDT 24
Peak memory 244012 kb
Host smart-78103f82-87e2-4eff-9fad-fc15cab25184
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000838448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.100083844
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.2785015944
Short name T582
Test name
Test status
Simulation time 4084952642 ps
CPU time 45.09 seconds
Started Aug 12 06:27:56 PM PDT 24
Finished Aug 12 06:28:41 PM PDT 24
Peak memory 261052 kb
Host smart-c4829c9f-dfe0-40de-bfa6-dfdc10b69bcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785015944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2
785015944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_key_error.1455286429
Short name T242
Test name
Test status
Simulation time 1381217135 ps
CPU time 4.45 seconds
Started Aug 12 06:28:02 PM PDT 24
Finished Aug 12 06:28:06 PM PDT 24
Peak memory 217812 kb
Host smart-cc66cd53-0155-4127-887a-a3f62035d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455286429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1455286429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.956179034
Short name T606
Test name
Test status
Simulation time 40023813 ps
CPU time 1.28 seconds
Started Aug 12 06:28:00 PM PDT 24
Finished Aug 12 06:28:01 PM PDT 24
Peak memory 223676 kb
Host smart-8b02b420-5049-49a0-b137-212cce91c47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956179034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.956179034 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1120899721
Short name T419
Test name
Test status
Simulation time 9588726369 ps
CPU time 940.5 seconds
Started Aug 12 06:27:58 PM PDT 24
Finished Aug 12 06:43:38 PM PDT 24
Peak memory 780680 kb
Host smart-a7e9c575-c5cb-4617-941f-e50799b20394
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120899721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.1120899721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2590130857
Short name T237
Test name
Test status
Simulation time 95361426797 ps
CPU time 409.86 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:34:47 PM PDT 24
Peak memory 571352 kb
Host smart-0e6b7ee3-8502-4e5e-b1dc-0927e236b84a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590130857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2590130857 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.3404729113
Short name T273
Test name
Test status
Simulation time 812978963 ps
CPU time 43.88 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:28:43 PM PDT 24
Peak memory 217864 kb
Host smart-028d2527-3855-4137-b6f0-a1210ab0b7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404729113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3404729113 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.2853123625
Short name T542
Test name
Test status
Simulation time 144596636136 ps
CPU time 1205.77 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:48:05 PM PDT 24
Peak memory 1481772 kb
Host smart-ea4f49c7-53ee-4fc8-b6e2-b103a95a47bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2853123625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2853123625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_alert_test.860142988
Short name T675
Test name
Test status
Simulation time 13602764 ps
CPU time 0.77 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:28:00 PM PDT 24
Peak memory 205020 kb
Host smart-15ff017d-2646-4ef8-a8ab-1ab4546d788c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860142988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.860142988 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.610982615
Short name T683
Test name
Test status
Simulation time 9177748478 ps
CPU time 120.54 seconds
Started Aug 12 06:27:58 PM PDT 24
Finished Aug 12 06:29:58 PM PDT 24
Peak memory 318768 kb
Host smart-f60bc79d-7f63-416b-969b-5eadecfc1538
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610982615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.610982615 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.824726719
Short name T587
Test name
Test status
Simulation time 4633555107 ps
CPU time 454.48 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:35:33 PM PDT 24
Peak memory 233584 kb
Host smart-a3373447-a93c-4a14-8905-1ff9982182a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824726719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.824726719
+enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.635100175
Short name T363
Test name
Test status
Simulation time 4530654743 ps
CPU time 206.95 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:31:26 PM PDT 24
Peak memory 310428 kb
Host smart-1fddcba0-e012-4b5d-a7e0-72418940b345
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635100175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.63
5100175 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.922842145
Short name T389
Test name
Test status
Simulation time 1120686324 ps
CPU time 80.14 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 06:29:19 PM PDT 24
Peak memory 271240 kb
Host smart-266aa3d2-b2a2-43d3-9083-ad6950417a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922842145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.922842145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.911463203
Short name T318
Test name
Test status
Simulation time 332815187 ps
CPU time 1.17 seconds
Started Aug 12 06:28:02 PM PDT 24
Finished Aug 12 06:28:03 PM PDT 24
Peak memory 217548 kb
Host smart-91039546-bff7-42d3-a645-fe5592b3bc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911463203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.911463203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.694243558
Short name T83
Test name
Test status
Simulation time 20731665648 ps
CPU time 2514.22 seconds
Started Aug 12 06:27:58 PM PDT 24
Finished Aug 12 07:09:52 PM PDT 24
Peak memory 1494820 kb
Host smart-b411fbbc-2a71-4e2c-8e06-291086f09dd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694243558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an
d_output.694243558 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.3954394228
Short name T451
Test name
Test status
Simulation time 2237012351 ps
CPU time 40.43 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:28:38 PM PDT 24
Peak memory 240284 kb
Host smart-e4d14a93-2289-4b36-b10c-a4e461fe1883
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954394228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3954394228 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1114175081
Short name T341
Test name
Test status
Simulation time 3609069133 ps
CPU time 45.49 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:28:43 PM PDT 24
Peak memory 218568 kb
Host smart-e5bd31b4-c339-42db-93ea-3e580262b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114175081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1114175081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.263961379
Short name T316
Test name
Test status
Simulation time 142127167271 ps
CPU time 2471.3 seconds
Started Aug 12 06:27:59 PM PDT 24
Finished Aug 12 07:09:11 PM PDT 24
Peak memory 1367676 kb
Host smart-5d1302c2-323d-4f43-9d7b-008dea3e8bf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=263961379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.263961379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_alert_test.4163848923
Short name T287
Test name
Test status
Simulation time 12223142 ps
CPU time 0.76 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:28:05 PM PDT 24
Peak memory 205240 kb
Host smart-57555a32-3143-4a41-8cac-f09dba7cbb82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163848923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.4163848923 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.1972427674
Short name T538
Test name
Test status
Simulation time 81358458062 ps
CPU time 224.18 seconds
Started Aug 12 06:28:02 PM PDT 24
Finished Aug 12 06:31:46 PM PDT 24
Peak memory 413808 kb
Host smart-04ece6ac-f7c6-415b-9882-8b3545bc5926
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972427674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1972427674 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.733862760
Short name T656
Test name
Test status
Simulation time 596213207 ps
CPU time 50.48 seconds
Started Aug 12 06:28:00 PM PDT 24
Finished Aug 12 06:28:50 PM PDT 24
Peak memory 217780 kb
Host smart-eeedf761-9435-4dff-b55d-9c7cf21e989b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733862760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.733862760
+enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.2480886913
Short name T203
Test name
Test status
Simulation time 2450843046 ps
CPU time 43.45 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:28:40 PM PDT 24
Peak memory 237924 kb
Host smart-7cf07a0e-1065-4e0f-b271-d5a240284cb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480886913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2
480886913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.3447727024
Short name T667
Test name
Test status
Simulation time 9719640939 ps
CPU time 280.03 seconds
Started Aug 12 06:28:01 PM PDT 24
Finished Aug 12 06:32:42 PM PDT 24
Peak memory 467580 kb
Host smart-ec26438c-1b62-423e-b482-746a7e5fe417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447727024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3447727024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.3712485799
Short name T387
Test name
Test status
Simulation time 677742323 ps
CPU time 3.93 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:28:01 PM PDT 24
Peak memory 217476 kb
Host smart-da07c154-9a5e-44c9-a452-0111dd13bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712485799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3712485799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.4252892334
Short name T309
Test name
Test status
Simulation time 49002562 ps
CPU time 1.05 seconds
Started Aug 12 06:27:56 PM PDT 24
Finished Aug 12 06:27:57 PM PDT 24
Peak memory 218872 kb
Host smart-6f473b2c-3ab2-4a2f-9cb1-c6899888ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252892334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.4252892334 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.1935298482
Short name T19
Test name
Test status
Simulation time 47355229487 ps
CPU time 2797.52 seconds
Started Aug 12 06:28:00 PM PDT 24
Finished Aug 12 07:14:38 PM PDT 24
Peak memory 1606940 kb
Host smart-34e79411-76ca-4399-9b97-4bb9833bc0df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935298482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.1935298482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.2314120507
Short name T677
Test name
Test status
Simulation time 71027862721 ps
CPU time 396.63 seconds
Started Aug 12 06:27:58 PM PDT 24
Finished Aug 12 06:34:34 PM PDT 24
Peak memory 555440 kb
Host smart-4df4f5d4-b5d2-40a1-a7c2-5b58cf2ea6fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314120507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2314120507 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.2184279991
Short name T223
Test name
Test status
Simulation time 54662126 ps
CPU time 1.22 seconds
Started Aug 12 06:27:57 PM PDT 24
Finished Aug 12 06:27:59 PM PDT 24
Peak memory 217904 kb
Host smart-d501c4ca-de18-4e16-b840-12a5a8f03054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184279991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2184279991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_alert_test.4132284735
Short name T490
Test name
Test status
Simulation time 12220105 ps
CPU time 0.79 seconds
Started Aug 12 06:28:09 PM PDT 24
Finished Aug 12 06:28:10 PM PDT 24
Peak memory 205080 kb
Host smart-b6f97ecb-a099-461f-8cf5-e7eb549534da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132284735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.4132284735 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1790896655
Short name T622
Test name
Test status
Simulation time 14871558932 ps
CPU time 170.18 seconds
Started Aug 12 06:28:06 PM PDT 24
Finished Aug 12 06:30:56 PM PDT 24
Peak memory 293796 kb
Host smart-88a48b73-8b70-4d25-ba90-20dae26228ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790896655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1790896655 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.3514150771
Short name T435
Test name
Test status
Simulation time 31797898435 ps
CPU time 300.21 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:33:05 PM PDT 24
Peak memory 234444 kb
Host smart-e0c52b32-99f0-47d8-87f5-1eb7256d172a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514150771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.351415077
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.3304971266
Short name T205
Test name
Test status
Simulation time 12166111301 ps
CPU time 205.03 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:31:29 PM PDT 24
Peak memory 404184 kb
Host smart-85186a4c-20ee-4933-84ea-7cdf4a620162
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304971266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3
304971266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2636827799
Short name T186
Test name
Test status
Simulation time 460792642 ps
CPU time 3.25 seconds
Started Aug 12 06:28:06 PM PDT 24
Finished Aug 12 06:28:09 PM PDT 24
Peak memory 218472 kb
Host smart-0f982fda-ada7-4d35-96fe-5e751071efdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636827799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2636827799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.949542406
Short name T60
Test name
Test status
Simulation time 1835104229 ps
CPU time 1.87 seconds
Started Aug 12 06:28:09 PM PDT 24
Finished Aug 12 06:28:11 PM PDT 24
Peak memory 217856 kb
Host smart-a4b5e734-1c46-4a4b-86dd-03df7643fd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949542406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.949542406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.3316606997
Short name T54
Test name
Test status
Simulation time 107913553 ps
CPU time 1.29 seconds
Started Aug 12 06:28:06 PM PDT 24
Finished Aug 12 06:28:08 PM PDT 24
Peak memory 219524 kb
Host smart-f272fb6b-0d86-4628-9d7d-7736bb10d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316606997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3316606997 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.13157863
Short name T279
Test name
Test status
Simulation time 4028576927 ps
CPU time 86.52 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:29:31 PM PDT 24
Peak memory 279412 kb
Host smart-df363bf7-8050-4ff8-b617-6d68ebb9d0ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13157863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and
_output.13157863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.3905608384
Short name T468
Test name
Test status
Simulation time 85061228337 ps
CPU time 490.51 seconds
Started Aug 12 06:28:05 PM PDT 24
Finished Aug 12 06:36:16 PM PDT 24
Peak memory 629808 kb
Host smart-0101af90-1529-44ce-b27c-cae1c5f5c418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905608384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3905608384 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.4012221222
Short name T343
Test name
Test status
Simulation time 7607250973 ps
CPU time 32.71 seconds
Started Aug 12 06:28:02 PM PDT 24
Finished Aug 12 06:28:34 PM PDT 24
Peak memory 218724 kb
Host smart-f4f35cdc-8362-4378-a361-ffc3b47bd4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012221222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.4012221222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.4220378124
Short name T208
Test name
Test status
Simulation time 14607936929 ps
CPU time 1339.35 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:50:24 PM PDT 24
Peak memory 719004 kb
Host smart-101c1723-9ac0-4564-a4f9-76296e05c73a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4220378124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4220378124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_alert_test.364807186
Short name T434
Test name
Test status
Simulation time 36699250 ps
CPU time 0.75 seconds
Started Aug 12 06:28:08 PM PDT 24
Finished Aug 12 06:28:09 PM PDT 24
Peak memory 205084 kb
Host smart-7eb6ddc8-9387-42bd-8d87-26f9f8d321a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364807186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.364807186 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.2883151015
Short name T502
Test name
Test status
Simulation time 4622979145 ps
CPU time 106.01 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:29:50 PM PDT 24
Peak memory 306996 kb
Host smart-cbc084e0-2099-40c8-8ce6-130593c9fc4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883151015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2883151015 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.1989075210
Short name T17
Test name
Test status
Simulation time 11696040763 ps
CPU time 529.11 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:36:53 PM PDT 24
Peak memory 237160 kb
Host smart-5b2b568d-5a07-4c5d-9aeb-e1599530255f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989075210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.198907521
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1452756290
Short name T13
Test name
Test status
Simulation time 1618166885 ps
CPU time 105.36 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:29:49 PM PDT 24
Peak memory 267640 kb
Host smart-b14d3db6-95ea-4ceb-86c3-b33a0d0f5b6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452756290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
452756290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.275178169
Short name T26
Test name
Test status
Simulation time 1930802701 ps
CPU time 155.48 seconds
Started Aug 12 06:28:05 PM PDT 24
Finished Aug 12 06:30:41 PM PDT 24
Peak memory 289364 kb
Host smart-6d534aab-b786-4974-851c-07d568da60c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275178169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.275178169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.4027932190
Short name T20
Test name
Test status
Simulation time 1118096128 ps
CPU time 6.21 seconds
Started Aug 12 06:28:06 PM PDT 24
Finished Aug 12 06:28:12 PM PDT 24
Peak memory 217732 kb
Host smart-5e420158-521e-480b-a75f-ec3b8b593fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027932190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.4027932190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.1374746223
Short name T34
Test name
Test status
Simulation time 117322437 ps
CPU time 1.64 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:28:06 PM PDT 24
Peak memory 223648 kb
Host smart-398a6fb1-714a-4943-a6ae-f01dfb6fd521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374746223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1374746223 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.2551597541
Short name T658
Test name
Test status
Simulation time 27402138544 ps
CPU time 3664.94 seconds
Started Aug 12 06:28:08 PM PDT 24
Finished Aug 12 07:29:14 PM PDT 24
Peak memory 1813668 kb
Host smart-107e5bf0-868d-4999-a90e-ce4b0626efc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551597541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.2551597541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.2864860219
Short name T164
Test name
Test status
Simulation time 13379144456 ps
CPU time 268.6 seconds
Started Aug 12 06:28:07 PM PDT 24
Finished Aug 12 06:32:36 PM PDT 24
Peak memory 334932 kb
Host smart-512820d2-ebc3-408b-b103-ee207139a609
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864860219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2864860219 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.31600796
Short name T573
Test name
Test status
Simulation time 150702355 ps
CPU time 4.19 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:28:08 PM PDT 24
Peak memory 218176 kb
Host smart-087f026c-56e2-448c-8063-1263496605e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31600796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.31600796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.1146956948
Short name T24
Test name
Test status
Simulation time 61620892280 ps
CPU time 1167.71 seconds
Started Aug 12 06:28:05 PM PDT 24
Finished Aug 12 06:47:32 PM PDT 24
Peak memory 632764 kb
Host smart-6d3810a1-a122-4c3d-8455-bfe7aab418f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1146956948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1146956948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_alert_test.3098665404
Short name T703
Test name
Test status
Simulation time 17289250 ps
CPU time 0.83 seconds
Started Aug 12 06:28:16 PM PDT 24
Finished Aug 12 06:28:17 PM PDT 24
Peak memory 205076 kb
Host smart-6e0060e1-fd94-4ec6-b043-c896a5c1aa92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098665404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3098665404 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.15376374
Short name T359
Test name
Test status
Simulation time 9656536657 ps
CPU time 235.48 seconds
Started Aug 12 06:28:07 PM PDT 24
Finished Aug 12 06:32:03 PM PDT 24
Peak memory 431740 kb
Host smart-b3a4f51d-22a7-4d0d-9128-666e27b5d0c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.15376374 +enable_masking=0
+sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.1460225756
Short name T241
Test name
Test status
Simulation time 6471898208 ps
CPU time 122.68 seconds
Started Aug 12 06:28:04 PM PDT 24
Finished Aug 12 06:30:07 PM PDT 24
Peak memory 223728 kb
Host smart-5889c7d1-78b7-4536-9065-fa480ff97873
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460225756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.146022575
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.1835761289
Short name T193
Test name
Test status
Simulation time 16711846447 ps
CPU time 226.62 seconds
Started Aug 12 06:28:13 PM PDT 24
Finished Aug 12 06:31:59 PM PDT 24
Peak memory 309340 kb
Host smart-ada0c6db-a99a-4c6c-87cf-a6d242c8df85
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835761289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1
835761289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.198293194
Short name T312
Test name
Test status
Simulation time 6631659752 ps
CPU time 177.27 seconds
Started Aug 12 06:28:11 PM PDT 24
Finished Aug 12 06:31:08 PM PDT 24
Peak memory 403312 kb
Host smart-90618ba7-1d21-4abf-b5e4-bc0a4d9bb30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198293194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.198293194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.3036169283
Short name T21
Test name
Test status
Simulation time 116726420 ps
CPU time 1.26 seconds
Started Aug 12 06:28:11 PM PDT 24
Finished Aug 12 06:28:12 PM PDT 24
Peak memory 217376 kb
Host smart-f9be43ea-8dcf-4553-b990-e8330ca7cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036169283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3036169283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.1927317162
Short name T462
Test name
Test status
Simulation time 473809084 ps
CPU time 4.28 seconds
Started Aug 12 06:28:10 PM PDT 24
Finished Aug 12 06:28:15 PM PDT 24
Peak memory 219752 kb
Host smart-21e565b8-cea2-438b-9ae5-88ff907b481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927317162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1927317162 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.2158387431
Short name T265
Test name
Test status
Simulation time 112981650365 ps
CPU time 1515.85 seconds
Started Aug 12 06:28:03 PM PDT 24
Finished Aug 12 06:53:19 PM PDT 24
Peak memory 1060232 kb
Host smart-eb3c522e-6774-4afe-8115-db0e0e3855ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158387431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.2158387431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.1013837090
Short name T358
Test name
Test status
Simulation time 6104898776 ps
CPU time 41.08 seconds
Started Aug 12 06:28:07 PM PDT 24
Finished Aug 12 06:28:48 PM PDT 24
Peak memory 255632 kb
Host smart-83ae3f21-b86f-44c0-9b45-50b117f3e61b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013837090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1013837090 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.3021048227
Short name T666
Test name
Test status
Simulation time 2092709740 ps
CPU time 28.31 seconds
Started Aug 12 06:28:09 PM PDT 24
Finished Aug 12 06:28:37 PM PDT 24
Peak memory 217724 kb
Host smart-d0a23b62-5776-44f8-bb16-136d5fd38ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021048227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.3021048227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.940599740
Short name T372
Test name
Test status
Simulation time 115339049380 ps
CPU time 836.27 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:42:08 PM PDT 24
Peak memory 1057580 kb
Host smart-ac785e19-ff23-4846-a153-f23068f4c342
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=940599740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.940599740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_alert_test.4270385174
Short name T428
Test name
Test status
Simulation time 35118460 ps
CPU time 0.74 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:28:13 PM PDT 24
Peak memory 204976 kb
Host smart-5b67a6c3-2607-43e2-8327-300863b0f8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270385174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.4270385174 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.3681739573
Short name T612
Test name
Test status
Simulation time 8723818468 ps
CPU time 231.51 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:32:03 PM PDT 24
Peak memory 407020 kb
Host smart-afa968ed-d8d9-4976-ae77-8eb18f8249df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681739573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3681739573 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.2046242300
Short name T355
Test name
Test status
Simulation time 93594781011 ps
CPU time 303.77 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:33:16 PM PDT 24
Peak memory 240412 kb
Host smart-0b95132a-98ec-458c-aa45-48a143e2829c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046242300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.204624230
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.2276347568
Short name T35
Test name
Test status
Simulation time 180733511190 ps
CPU time 335.83 seconds
Started Aug 12 06:28:15 PM PDT 24
Finished Aug 12 06:33:51 PM PDT 24
Peak memory 438124 kb
Host smart-6eb736fe-339c-45f6-abfb-1f79c0951ba2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276347568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2
276347568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.2304322809
Short name T660
Test name
Test status
Simulation time 22789002216 ps
CPU time 180.1 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:31:12 PM PDT 24
Peak memory 396148 kb
Host smart-d975d79e-dc7c-4486-9529-9756506540fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304322809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2304322809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1056600610
Short name T399
Test name
Test status
Simulation time 4090197472 ps
CPU time 7.56 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:28:20 PM PDT 24
Peak memory 217980 kb
Host smart-32dc72b9-46c7-466b-8b23-db12a455e58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056600610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1056600610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.430097989
Short name T717
Test name
Test status
Simulation time 67524387 ps
CPU time 1.23 seconds
Started Aug 12 06:28:14 PM PDT 24
Finished Aug 12 06:28:16 PM PDT 24
Peak memory 218992 kb
Host smart-08c036be-6207-45f9-b96e-3b7fa147d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430097989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.430097989 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.2841474572
Short name T650
Test name
Test status
Simulation time 175845257783 ps
CPU time 3298.97 seconds
Started Aug 12 06:28:10 PM PDT 24
Finished Aug 12 07:23:10 PM PDT 24
Peak memory 1747884 kb
Host smart-35d54057-0f6b-487b-91c4-49be3f7a9470
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841474572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.2841474572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.3770386673
Short name T68
Test name
Test status
Simulation time 18755323213 ps
CPU time 218.49 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:31:51 PM PDT 24
Peak memory 424388 kb
Host smart-977de721-743c-462b-b55a-2843dce173ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770386673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3770386673 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.1739670154
Short name T549
Test name
Test status
Simulation time 355706400 ps
CPU time 7.35 seconds
Started Aug 12 06:28:11 PM PDT 24
Finished Aug 12 06:28:19 PM PDT 24
Peak memory 219624 kb
Host smart-89d10823-77d0-408b-9538-93ce44935a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739670154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1739670154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.1424376446
Short name T629
Test name
Test status
Simulation time 7531532367 ps
CPU time 180.4 seconds
Started Aug 12 06:28:14 PM PDT 24
Finished Aug 12 06:31:15 PM PDT 24
Peak memory 330708 kb
Host smart-88a2c0fe-031a-44dc-bf72-ca81456b77fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1424376446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1424376446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_alert_test.2879014521
Short name T486
Test name
Test status
Simulation time 48542982 ps
CPU time 0.77 seconds
Started Aug 12 06:28:21 PM PDT 24
Finished Aug 12 06:28:22 PM PDT 24
Peak memory 205040 kb
Host smart-5d4fdffd-3601-42a9-bf8d-05e00059be11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879014521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2879014521 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1109961389
Short name T676
Test name
Test status
Simulation time 9624694356 ps
CPU time 197.11 seconds
Started Aug 12 06:28:14 PM PDT 24
Finished Aug 12 06:31:31 PM PDT 24
Peak memory 417316 kb
Host smart-d706ee7f-5493-4704-bec0-ade6f05d7af8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109961389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1109961389 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.1099706264
Short name T133
Test name
Test status
Simulation time 86612164412 ps
CPU time 375.02 seconds
Started Aug 12 06:28:12 PM PDT 24
Finished Aug 12 06:34:27 PM PDT 24
Peak memory 236360 kb
Host smart-9089272e-5a44-4b60-9109-97e9363cdf93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099706264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.109970626
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.2390196103
Short name T350
Test name
Test status
Simulation time 13942259027 ps
CPU time 267.2 seconds
Started Aug 12 06:28:11 PM PDT 24
Finished Aug 12 06:32:39 PM PDT 24
Peak memory 439244 kb
Host smart-7969607c-f368-450f-9cec-4b11267f96a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390196103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2
390196103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.1693979718
Short name T322
Test name
Test status
Simulation time 5629242595 ps
CPU time 15.35 seconds
Started Aug 12 06:28:14 PM PDT 24
Finished Aug 12 06:28:30 PM PDT 24
Peak memory 240456 kb
Host smart-e6a0d3e4-02a8-4d49-acf6-8be678279d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693979718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1693979718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.3496075641
Short name T268
Test name
Test status
Simulation time 1642383587 ps
CPU time 5.5 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:28:25 PM PDT 24
Peak memory 217400 kb
Host smart-84d39b14-6686-42c3-bbc9-cbbb0e209073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496075641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3496075641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.4035882171
Short name T6
Test name
Test status
Simulation time 692592513 ps
CPU time 12.08 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:28:31 PM PDT 24
Peak memory 234840 kb
Host smart-319f421b-3cb4-4eec-9faf-476fc492809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035882171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.4035882171 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.3576802581
Short name T194
Test name
Test status
Simulation time 45382860661 ps
CPU time 1337.01 seconds
Started Aug 12 06:28:14 PM PDT 24
Finished Aug 12 06:50:31 PM PDT 24
Peak memory 991136 kb
Host smart-62e28cc5-2117-4766-87a6-4e0b92f10a48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576802581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.3576802581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.2797204394
Short name T611
Test name
Test status
Simulation time 7458164225 ps
CPU time 47.09 seconds
Started Aug 12 06:28:13 PM PDT 24
Finished Aug 12 06:29:01 PM PDT 24
Peak memory 252948 kb
Host smart-c8d2268a-d2ed-4e4a-ba40-12ba1fe2cf21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797204394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2797204394 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.654077010
Short name T678
Test name
Test status
Simulation time 674701838 ps
CPU time 32.66 seconds
Started Aug 12 06:28:14 PM PDT 24
Finished Aug 12 06:28:47 PM PDT 24
Peak memory 218172 kb
Host smart-faa3ca46-c41d-4acf-88a0-eecdc4c2b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654077010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.654077010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.805072216
Short name T713
Test name
Test status
Simulation time 8055742898 ps
CPU time 148.64 seconds
Started Aug 12 06:28:18 PM PDT 24
Finished Aug 12 06:30:47 PM PDT 24
Peak memory 314340 kb
Host smart-409015b2-fbfa-4333-a1e3-03e6177e3f28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=805072216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.805072216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1433142302
Short name T190
Test name
Test status
Simulation time 19941384 ps
CPU time 0.79 seconds
Started Aug 12 06:28:18 PM PDT 24
Finished Aug 12 06:28:19 PM PDT 24
Peak memory 205108 kb
Host smart-62f61cca-8faa-4330-a7a6-36b0e95137f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433142302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1433142302 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.3358319310
Short name T463
Test name
Test status
Simulation time 51641284569 ps
CPU time 319.74 seconds
Started Aug 12 06:28:20 PM PDT 24
Finished Aug 12 06:33:40 PM PDT 24
Peak memory 509664 kb
Host smart-3237f0e7-ca7e-4db8-8187-46f86c2d893c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358319310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3358319310 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.2839673966
Short name T323
Test name
Test status
Simulation time 25544225618 ps
CPU time 807.46 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:41:47 PM PDT 24
Peak memory 252268 kb
Host smart-29d928c1-8f78-408b-bf98-19ac5b450723
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839673966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.283967396
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.4243707982
Short name T25
Test name
Test status
Simulation time 36902472291 ps
CPU time 296.19 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:33:15 PM PDT 24
Peak memory 333216 kb
Host smart-082c2b95-1093-482f-a9c8-2f2aea6c6531
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243707982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.4
243707982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.2799985223
Short name T143
Test name
Test status
Simulation time 7311272980 ps
CPU time 252.87 seconds
Started Aug 12 06:28:17 PM PDT 24
Finished Aug 12 06:32:30 PM PDT 24
Peak memory 335112 kb
Host smart-9a795a99-c258-4cf5-b5ee-df60853ba06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799985223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2799985223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.2649282522
Short name T303
Test name
Test status
Simulation time 1065289032 ps
CPU time 3.33 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:28:22 PM PDT 24
Peak memory 219072 kb
Host smart-cff75995-4ff2-4494-b815-72c0a75ffea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649282522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2649282522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3965006315
Short name T505
Test name
Test status
Simulation time 37747377 ps
CPU time 1.45 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:28:20 PM PDT 24
Peak memory 217188 kb
Host smart-81719ac8-a45e-4c0d-9946-8c623b3d1a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965006315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3965006315 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.2653137897
Short name T306
Test name
Test status
Simulation time 264762626341 ps
CPU time 403.81 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:35:03 PM PDT 24
Peak memory 706276 kb
Host smart-574d13d0-df4c-4929-9138-c60b9dbbad1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653137897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.2653137897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.2474699471
Short name T188
Test name
Test status
Simulation time 8464648697 ps
CPU time 196.24 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:31:35 PM PDT 24
Peak memory 295792 kb
Host smart-835601b3-2a4d-40a2-83de-43ede10b9205
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474699471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2474699471 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.2143575695
Short name T704
Test name
Test status
Simulation time 831312448 ps
CPU time 14.44 seconds
Started Aug 12 06:28:19 PM PDT 24
Finished Aug 12 06:28:34 PM PDT 24
Peak memory 217760 kb
Host smart-77ce5d07-5cf2-4173-b0ae-aad67fc9fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143575695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2143575695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.3379363323
Short name T417
Test name
Test status
Simulation time 58600872676 ps
CPU time 1580.04 seconds
Started Aug 12 06:28:18 PM PDT 24
Finished Aug 12 06:54:39 PM PDT 24
Peak memory 681456 kb
Host smart-26cb68c2-f57a-4397-919e-ee429b2a37a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3379363323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3379363323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_alert_test.3804483103
Short name T216
Test name
Test status
Simulation time 18956071 ps
CPU time 0.81 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:26:38 PM PDT 24
Peak memory 205092 kb
Host smart-6a058517-874c-4fa2-80a6-f279bc6cf33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804483103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3804483103 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.1677806625
Short name T716
Test name
Test status
Simulation time 15183078862 ps
CPU time 194.16 seconds
Started Aug 12 06:26:28 PM PDT 24
Finished Aug 12 06:29:42 PM PDT 24
Peak memory 396404 kb
Host smart-a04b9706-544d-495d-b692-f5e641412562
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677806625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1677806625 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.1220490006
Short name T187
Test name
Test status
Simulation time 327756814 ps
CPU time 1.4 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:26:44 PM PDT 24
Peak memory 218492 kb
Host smart-c8093c9c-a20a-4f6b-92bd-ef788e194384
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220490006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_par
tial_data.1220490006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.549102784
Short name T709
Test name
Test status
Simulation time 8321688324 ps
CPU time 214.19 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:30:15 PM PDT 24
Peak memory 226492 kb
Host smart-1a099907-97b1-4685-9968-82eecd7753d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549102784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.549102784 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.3779858502
Short name T438
Test name
Test status
Simulation time 1466763909 ps
CPU time 24.08 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:27:07 PM PDT 24
Peak memory 223644 kb
Host smart-0ea4f164-0076-4832-bd24-d347b9cf2bbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3779858502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3779858502 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1108052212
Short name T326
Test name
Test status
Simulation time 1432403698 ps
CPU time 9.95 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:26:54 PM PDT 24
Peak memory 223616 kb
Host smart-f707dc78-4e5a-4939-a901-91f15e688c51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1108052212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1108052212 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.1546748985
Short name T302
Test name
Test status
Simulation time 16644996002 ps
CPU time 35.02 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:27:18 PM PDT 24
Peak memory 218144 kb
Host smart-e8342c62-a5c6-410c-88d5-34986fade578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546748985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1546748985 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.518408871
Short name T686
Test name
Test status
Simulation time 13424322048 ps
CPU time 180.76 seconds
Started Aug 12 06:26:39 PM PDT 24
Finished Aug 12 06:29:40 PM PDT 24
Peak memory 294492 kb
Host smart-5e3cd9e7-0652-4a93-96f5-65e0eb38cad8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518408871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.518
408871 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.2292243735
Short name T342
Test name
Test status
Simulation time 1109206020 ps
CPU time 44.96 seconds
Started Aug 12 06:26:35 PM PDT 24
Finished Aug 12 06:27:20 PM PDT 24
Peak memory 248572 kb
Host smart-0adcc020-22e8-4bc2-9375-939cd5f0e9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292243735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2292243735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.1958803831
Short name T55
Test name
Test status
Simulation time 684634703 ps
CPU time 3.74 seconds
Started Aug 12 06:26:32 PM PDT 24
Finished Aug 12 06:26:35 PM PDT 24
Peak memory 217516 kb
Host smart-d8086d98-5d51-4139-a5ec-421dd6082fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958803831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1958803831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.173589426
Short name T52
Test name
Test status
Simulation time 142631731 ps
CPU time 1.28 seconds
Started Aug 12 06:26:33 PM PDT 24
Finished Aug 12 06:26:34 PM PDT 24
Peak memory 217884 kb
Host smart-0615b500-3922-401a-b839-484525f62ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173589426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.173589426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1309092376
Short name T198
Test name
Test status
Simulation time 757873145661 ps
CPU time 2003.29 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 07:00:06 PM PDT 24
Peak memory 2017148 kb
Host smart-c871577a-74da-4b16-b716-7777c9d4fd20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309092376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1309092376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.2192493768
Short name T23
Test name
Test status
Simulation time 11404114366 ps
CPU time 249.38 seconds
Started Aug 12 06:26:45 PM PDT 24
Finished Aug 12 06:30:54 PM PDT 24
Peak memory 461520 kb
Host smart-3481dd1a-f91d-4863-b25d-d1a822ca929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192493768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2192493768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.2002149716
Short name T602
Test name
Test status
Simulation time 19898561717 ps
CPU time 395.26 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:33:17 PM PDT 24
Peak memory 611420 kb
Host smart-9847310f-b11f-4567-b358-5f22392ad2f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002149716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2002149716 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.3684095645
Short name T61
Test name
Test status
Simulation time 3362750246 ps
CPU time 38.54 seconds
Started Aug 12 06:26:27 PM PDT 24
Finished Aug 12 06:27:06 PM PDT 24
Peak memory 217828 kb
Host smart-818f5c3b-eb57-46a1-a0f5-4e9fad190ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684095645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3684095645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.1585429826
Short name T471
Test name
Test status
Simulation time 40962075657 ps
CPU time 969.4 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:42:53 PM PDT 24
Peak memory 549116 kb
Host smart-d407addb-ff00-4cf1-b339-369c8945a76e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1585429826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1585429826 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_alert_test.4163224565
Short name T332
Test name
Test status
Simulation time 18656736 ps
CPU time 0.79 seconds
Started Aug 12 06:26:45 PM PDT 24
Finished Aug 12 06:26:46 PM PDT 24
Peak memory 205120 kb
Host smart-d5ffa1d5-6841-4122-99d2-610ed232e782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163224565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.4163224565 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.1978976648
Short name T690
Test name
Test status
Simulation time 5810769109 ps
CPU time 60.58 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 278952 kb
Host smart-0344ce7c-2c20-45a3-aae8-7d009b874391
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978976648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1978976648 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.3304515116
Short name T228
Test name
Test status
Simulation time 62026433460 ps
CPU time 314.29 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:31:55 PM PDT 24
Peak memory 483960 kb
Host smart-176e053e-372e-44a0-9cf1-5415d0ad9f30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304515116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.3304515116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.2492201058
Short name T151
Test name
Test status
Simulation time 33317074428 ps
CPU time 720.35 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:38:37 PM PDT 24
Peak memory 241768 kb
Host smart-6c98a0e1-8e85-4305-b9cf-3a57f7f2841e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492201058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2492201058
+enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.1249557481
Short name T476
Test name
Test status
Simulation time 850778831 ps
CPU time 15.56 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:46 PM PDT 24
Peak memory 223676 kb
Host smart-7b75be51-da0f-454e-9a59-524898caee8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1249557481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1249557481 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.257431864
Short name T404
Test name
Test status
Simulation time 4983492892 ps
CPU time 10.27 seconds
Started Aug 12 06:26:39 PM PDT 24
Finished Aug 12 06:26:49 PM PDT 24
Peak memory 223664 kb
Host smart-5c9857f3-6440-49c5-901e-98a71c2e8e54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=257431864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.257431864 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1385903536
Short name T718
Test name
Test status
Simulation time 15333693717 ps
CPU time 78.5 seconds
Started Aug 12 06:26:36 PM PDT 24
Finished Aug 12 06:27:54 PM PDT 24
Peak memory 218296 kb
Host smart-7751f86e-5949-475c-95fc-a859659f312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385903536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1385903536 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.1167253221
Short name T613
Test name
Test status
Simulation time 19179548732 ps
CPU time 83.74 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:28:01 PM PDT 24
Peak memory 284872 kb
Host smart-c146459d-1b66-4bfc-aa31-07e1672fab63
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167253221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.11
67253221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3329157543
Short name T481
Test name
Test status
Simulation time 2724106914 ps
CPU time 195.15 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:29:53 PM PDT 24
Peak memory 322092 kb
Host smart-8505d56c-622f-4af5-b891-725d8a9bad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329157543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3329157543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.2813864340
Short name T578
Test name
Test status
Simulation time 10295649244 ps
CPU time 11.35 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:26:54 PM PDT 24
Peak memory 218976 kb
Host smart-06aecd0d-2b5a-4b52-bf8e-f269190e302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813864340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2813864340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.683129022
Short name T244
Test name
Test status
Simulation time 62381619 ps
CPU time 1.21 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:26:44 PM PDT 24
Peak memory 217284 kb
Host smart-57801187-bcf8-46e8-942a-4577b0d2f49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683129022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.683129022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.1394093173
Short name T335
Test name
Test status
Simulation time 21905126059 ps
CPU time 826.26 seconds
Started Aug 12 06:26:37 PM PDT 24
Finished Aug 12 06:40:24 PM PDT 24
Peak memory 1199996 kb
Host smart-c10327e2-b6df-47d9-91db-ecc6184c84f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394093173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.1394093173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1344907405
Short name T345
Test name
Test status
Simulation time 35030760493 ps
CPU time 261.21 seconds
Started Aug 12 06:26:38 PM PDT 24
Finished Aug 12 06:31:00 PM PDT 24
Peak memory 447036 kb
Host smart-7be213c0-bbe0-49be-81b8-c5460caf65eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344907405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1344907405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.1459485582
Short name T128
Test name
Test status
Simulation time 5791214289 ps
CPU time 166.99 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:29:27 PM PDT 24
Peak memory 370028 kb
Host smart-d11cab03-d024-48ce-81bc-b5a0dda84240
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459485582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1459485582 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.4225927464
Short name T408
Test name
Test status
Simulation time 788452549 ps
CPU time 20.66 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 218032 kb
Host smart-f9ce0bf4-ec0e-413d-981a-d505e4626c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225927464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.4225927464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3776864336
Short name T247
Test name
Test status
Simulation time 87033534 ps
CPU time 0.88 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:26:45 PM PDT 24
Peak memory 205096 kb
Host smart-5320634f-7b05-4812-95cf-2541daabc1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776864336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3776864336 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.3728609706
Short name T640
Test name
Test status
Simulation time 59127583423 ps
CPU time 236.48 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:30:36 PM PDT 24
Peak memory 314080 kb
Host smart-f9dbfb88-ab75-4f6c-b205-a97b99c79425
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728609706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3728609706 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1361078552
Short name T141
Test name
Test status
Simulation time 6124156549 ps
CPU time 106.79 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:28:31 PM PDT 24
Peak memory 303680 kb
Host smart-cd36d56c-b1aa-4ee7-821e-888286aef86a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361078552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.1361078552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.1659735796
Short name T180
Test name
Test status
Simulation time 74996484230 ps
CPU time 735.84 seconds
Started Aug 12 06:26:38 PM PDT 24
Finished Aug 12 06:38:54 PM PDT 24
Peak memory 251936 kb
Host smart-8e6d5638-5956-42f4-9bbd-44efaa284418
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659735796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1659735796
+enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.913033950
Short name T487
Test name
Test status
Simulation time 3753934011 ps
CPU time 20.58 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:27:04 PM PDT 24
Peak memory 223728 kb
Host smart-3c7252cd-dbb4-4272-af58-c5417aac86bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=913033950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.913033950 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.1943249162
Short name T319
Test name
Test status
Simulation time 3689499634 ps
CPU time 39.71 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:27:24 PM PDT 24
Peak memory 223596 kb
Host smart-c0f7e21e-281e-4dbd-85fa-42d00b43c38b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1943249162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1943249162 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.4005766391
Short name T42
Test name
Test status
Simulation time 6150099082 ps
CPU time 50.2 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:27:32 PM PDT 24
Peak memory 218052 kb
Host smart-1d03b9d2-aa64-492d-b566-4abd2dddac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005766391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.4005766391 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.2749770189
Short name T668
Test name
Test status
Simulation time 4430525475 ps
CPU time 153.75 seconds
Started Aug 12 06:26:34 PM PDT 24
Finished Aug 12 06:29:08 PM PDT 24
Peak memory 285696 kb
Host smart-4f1b938d-1c26-4a40-9c18-9ce041854379
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749770189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.27
49770189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.3023084921
Short name T532
Test name
Test status
Simulation time 18278692100 ps
CPU time 277.6 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:31:22 PM PDT 24
Peak memory 474032 kb
Host smart-71dfc1ce-8e37-41d3-8900-73e638804784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023084921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3023084921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.4226813703
Short name T41
Test name
Test status
Simulation time 6884801160 ps
CPU time 8.24 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:26:49 PM PDT 24
Peak memory 217892 kb
Host smart-b4f0bd24-b553-4126-aeb7-b1cbf0795043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226813703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.4226813703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1524791050
Short name T376
Test name
Test status
Simulation time 28701490 ps
CPU time 1.23 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:26:46 PM PDT 24
Peak memory 218548 kb
Host smart-d69eddbf-c6de-4882-8117-4dd6d4d2abec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524791050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1524791050 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2863367062
Short name T413
Test name
Test status
Simulation time 56011854529 ps
CPU time 3760.15 seconds
Started Aug 12 06:26:39 PM PDT 24
Finished Aug 12 07:29:20 PM PDT 24
Peak memory 1960924 kb
Host smart-985c5f7f-0fe4-4c53-aeff-cb2d45e6b3bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863367062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2863367062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.3857477554
Short name T507
Test name
Test status
Simulation time 142291684699 ps
CPU time 368.16 seconds
Started Aug 12 06:26:39 PM PDT 24
Finished Aug 12 06:32:48 PM PDT 24
Peak memory 537956 kb
Host smart-00c7428f-a41a-4038-b961-362fdef24d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857477554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3857477554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.649108246
Short name T18
Test name
Test status
Simulation time 21915077880 ps
CPU time 291.46 seconds
Started Aug 12 06:26:34 PM PDT 24
Finished Aug 12 06:31:26 PM PDT 24
Peak memory 498224 kb
Host smart-ca068a86-c5b1-457f-b534-f4147fa37ac7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649108246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.649108246 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.4240510825
Short name T348
Test name
Test status
Simulation time 679114015 ps
CPU time 11.56 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 221456 kb
Host smart-2829f7ca-b288-422d-b91d-0c99508d87ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240510825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.4240510825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1757226425
Short name T276
Test name
Test status
Simulation time 31595130860 ps
CPU time 813.79 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:40:20 PM PDT 24
Peak memory 734600 kb
Host smart-26138854-4a6e-4c59-b405-185efa2a4fcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1757226425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1757226425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_alert_test.63810316
Short name T605
Test name
Test status
Simulation time 98663913 ps
CPU time 0.87 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 06:26:48 PM PDT 24
Peak memory 205016 kb
Host smart-49f99b67-7fd7-4995-b42b-f733701b9dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63810316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.63810316 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.1033178680
Short name T591
Test name
Test status
Simulation time 34218706647 ps
CPU time 179.46 seconds
Started Aug 12 06:26:41 PM PDT 24
Finished Aug 12 06:29:41 PM PDT 24
Peak memory 366600 kb
Host smart-95af27f2-2730-4bcf-915d-8b85edded2bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033178680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1033178680 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2587134689
Short name T72
Test name
Test status
Simulation time 36733464148 ps
CPU time 581.77 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:36:26 PM PDT 24
Peak memory 246772 kb
Host smart-b4b01b51-dfdf-493f-955d-dc612b27777c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587134689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2587134689
+enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.1916463346
Short name T266
Test name
Test status
Simulation time 2275302736 ps
CPU time 45.03 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:27:27 PM PDT 24
Peak memory 221224 kb
Host smart-96985bab-bfc9-46e6-bab0-178ac9658e85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1916463346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1916463346 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.3389106489
Short name T448
Test name
Test status
Simulation time 1727315718 ps
CPU time 32.96 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:27:15 PM PDT 24
Peak memory 228240 kb
Host smart-7712e047-e195-413f-9502-a54f49729917
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3389106489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3389106489 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.3666395274
Short name T243
Test name
Test status
Simulation time 27310982376 ps
CPU time 170.3 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:29:37 PM PDT 24
Peak memory 349836 kb
Host smart-60028e24-f8e8-46da-8d8a-369e472c35ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666395274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.36
66395274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.3598617631
Short name T437
Test name
Test status
Simulation time 18121255519 ps
CPU time 370.55 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:32:55 PM PDT 24
Peak memory 386940 kb
Host smart-303243ae-493b-4113-9b9b-ea8dbce66f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598617631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3598617631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1464506002
Short name T375
Test name
Test status
Simulation time 5862713051 ps
CPU time 7.97 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:26:54 PM PDT 24
Peak memory 217844 kb
Host smart-e2ff7549-4789-430e-969e-acadb597c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464506002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1464506002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.2925197989
Short name T494
Test name
Test status
Simulation time 43044366 ps
CPU time 1.25 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 06:26:49 PM PDT 24
Peak memory 219004 kb
Host smart-767f151c-57de-4a59-8ee3-56e53d8d085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925197989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2925197989 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.4009327351
Short name T646
Test name
Test status
Simulation time 99815114278 ps
CPU time 3649.23 seconds
Started Aug 12 06:26:48 PM PDT 24
Finished Aug 12 07:27:38 PM PDT 24
Peak memory 3130216 kb
Host smart-d1d4b908-7cee-4f99-b6ec-a2ed5873296e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009327351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.4009327351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.1334879490
Short name T580
Test name
Test status
Simulation time 7748481587 ps
CPU time 75.83 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:28:00 PM PDT 24
Peak memory 288884 kb
Host smart-60615135-1f5b-461a-ade7-d339232ebb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334879490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1334879490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.673215238
Short name T424
Test name
Test status
Simulation time 37568683693 ps
CPU time 345.25 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:32:25 PM PDT 24
Peak memory 546480 kb
Host smart-8111126e-b6f9-43f1-a8cf-1adfc4a1ad2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673215238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.673215238 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.2303804846
Short name T284
Test name
Test status
Simulation time 5465320151 ps
CPU time 8.78 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:26:51 PM PDT 24
Peak memory 218256 kb
Host smart-f04a29d0-bedb-4b1b-a2a6-8e2fc0037682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303804846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2303804846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.3363375809
Short name T662
Test name
Test status
Simulation time 10789635315 ps
CPU time 214.66 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:30:15 PM PDT 24
Peak memory 353916 kb
Host smart-ba50951c-8933-4c85-9698-ead78d1b8950
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3363375809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3363375809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_alert_test.2643408323
Short name T278
Test name
Test status
Simulation time 50387232 ps
CPU time 0.74 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 06:26:48 PM PDT 24
Peak memory 205068 kb
Host smart-c34b8aa4-08fb-4a69-bae2-27a3eaa5786d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643408323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2643408323 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.467649738
Short name T381
Test name
Test status
Simulation time 16511205765 ps
CPU time 340.26 seconds
Started Aug 12 06:26:50 PM PDT 24
Finished Aug 12 06:32:30 PM PDT 24
Peak memory 542032 kb
Host smart-d17ceea9-4bb6-494c-a98a-ced68d86104f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467649738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.467649738 +enable_masking=0
+sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.2007565338
Short name T402
Test name
Test status
Simulation time 10783226728 ps
CPU time 235.47 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 06:30:43 PM PDT 24
Peak memory 412180 kb
Host smart-fe539bef-2142-45e0-bf64-4c46bd3a9f00
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007565338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.2007565338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.278762088
Short name T674
Test name
Test status
Simulation time 5397703931 ps
CPU time 142.42 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:29:08 PM PDT 24
Peak memory 222904 kb
Host smart-2c070a4f-4353-498d-b0e3-83501a850c09
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278762088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.278762088 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.3999269444
Short name T331
Test name
Test status
Simulation time 55133602 ps
CPU time 4.3 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:26:49 PM PDT 24
Peak memory 216508 kb
Host smart-6ce6dd4a-33f3-4a47-87b3-a6879875e862
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3999269444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3999269444 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.2665113367
Short name T530
Test name
Test status
Simulation time 311606790 ps
CPU time 8.96 seconds
Started Aug 12 06:26:42 PM PDT 24
Finished Aug 12 06:26:51 PM PDT 24
Peak memory 221396 kb
Host smart-3bfd197a-7e3c-4b9d-8538-b4404c5e6845
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2665113367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2665113367 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.2626075873
Short name T67
Test name
Test status
Simulation time 28506504150 ps
CPU time 51.5 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 06:27:39 PM PDT 24
Peak memory 218336 kb
Host smart-9546d730-7335-4285-acd6-a6e720b02043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626075873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2626075873 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.2804940168
Short name T544
Test name
Test status
Simulation time 23617262544 ps
CPU time 272.63 seconds
Started Aug 12 06:26:44 PM PDT 24
Finished Aug 12 06:31:17 PM PDT 24
Peak memory 319552 kb
Host smart-859eaf8a-b01a-4f2f-a6cf-3c5b6fe3ddba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804940168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.28
04940168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.652210188
Short name T575
Test name
Test status
Simulation time 13003109073 ps
CPU time 251.28 seconds
Started Aug 12 06:26:36 PM PDT 24
Finished Aug 12 06:30:48 PM PDT 24
Peak memory 339280 kb
Host smart-3297b1f0-1224-409b-9b9c-4f25e2213b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652210188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.652210188 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.303749087
Short name T320
Test name
Test status
Simulation time 1663059071 ps
CPU time 8.66 seconds
Started Aug 12 06:26:48 PM PDT 24
Finished Aug 12 06:26:56 PM PDT 24
Peak memory 217748 kb
Host smart-1c1650d4-7e30-4f33-b751-c35b3b3d2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303749087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.303749087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.4009805119
Short name T367
Test name
Test status
Simulation time 45045770 ps
CPU time 1.22 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:26:45 PM PDT 24
Peak memory 217200 kb
Host smart-f1fe9314-34cd-4d6a-b764-fb859ca32d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009805119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.4009805119 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.1587419163
Short name T509
Test name
Test status
Simulation time 49925274066 ps
CPU time 3072.77 seconds
Started Aug 12 06:26:47 PM PDT 24
Finished Aug 12 07:18:00 PM PDT 24
Peak memory 1736584 kb
Host smart-0fc8f368-2ae0-4869-87ab-11b8351ccd51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587419163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.1587419163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.1983344331
Short name T385
Test name
Test status
Simulation time 12685898077 ps
CPU time 304.44 seconds
Started Aug 12 06:26:40 PM PDT 24
Finished Aug 12 06:31:44 PM PDT 24
Peak memory 490544 kb
Host smart-40fa08ca-66eb-4dac-8a4c-ffafff560396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983344331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1983344331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.679057926
Short name T337
Test name
Test status
Simulation time 3073242574 ps
CPU time 231.46 seconds
Started Aug 12 06:26:39 PM PDT 24
Finished Aug 12 06:30:31 PM PDT 24
Peak memory 324040 kb
Host smart-2615f7eb-931d-4db9-a8bc-fda2feb59569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679057926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.679057926 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.895268381
Short name T545
Test name
Test status
Simulation time 1035029289 ps
CPU time 47.63 seconds
Started Aug 12 06:26:43 PM PDT 24
Finished Aug 12 06:27:31 PM PDT 24
Peak memory 223556 kb
Host smart-758a1b9e-dc9a-49a4-97e5-9efd90578cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895268381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.895268381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.934199153
Short name T699
Test name
Test status
Simulation time 27917983814 ps
CPU time 414.75 seconds
Started Aug 12 06:26:46 PM PDT 24
Finished Aug 12 06:33:40 PM PDT 24
Peak memory 348620 kb
Host smart-27180a5c-ed4a-491f-9092-906d57f17a34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=934199153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.934199153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest
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