Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16218456	1			T1	9246		T2	1262		T3	1832
all_values[1]	16218456	1			T1	9246		T2	1262		T3	1832
all_values[2]	16218456	1			T1	9246		T2	1262		T3	1832

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

458618

1

T1

126

T2

56

T12

3618

auto[1]

48196750

1

T1

27612

T2

3730

T3

5496

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48437043

1

T1

27261

T2

3390

T3

4677

auto[1]

218325

1

T1

477

T2

396

T3

819

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	160206	1			T1	8		T12	216		T13	1
all_values[0]	auto[0]	auto[1]	1215	1			T1	4		T12	2		T15	6
all_values[0]	auto[1]	auto[0]	15985475	1			T1	9079		T2	1130		T3	1559
all_values[0]	auto[1]	auto[1]	71560	1			T1	155		T2	132		T3	273
all_values[1]	auto[0]	auto[0]	135057	1			T1	86		T12	216		T15	102
all_values[1]	auto[0]	auto[1]	824	1			T1	5		T12	2		T15	4
all_values[1]	auto[1]	auto[0]	16010624	1			T1	9001		T2	1130		T3	1559
all_values[1]	auto[1]	auto[1]	71951	1			T1	154		T2	132		T3	273
all_values[2]	auto[0]	auto[0]	160379	1			T1	22		T2	53		T12	3168
all_values[2]	auto[0]	auto[1]	937	1			T1	1		T2	3		T12	14
all_values[2]	auto[1]	auto[0]	15985302	1			T1	9065		T2	1077		T3	1559
all_values[2]	auto[1]	auto[1]	71838	1			T1	158		T2	129		T3	273