Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49182 |
1 |
|
|
T1 |
80 |
|
T2 |
2 |
|
T3 |
350 |
auto[1] |
61600 |
1 |
|
|
T1 |
190 |
|
T2 |
166 |
|
T12 |
374 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27439 |
1 |
|
|
T1 |
55 |
|
T2 |
51 |
|
T3 |
115 |
lower_val |
27428 |
1 |
|
|
T1 |
57 |
|
T2 |
44 |
|
T3 |
80 |
zero_val |
805 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
55670 |
1 |
|
|
T1 |
144 |
|
T2 |
82 |
|
T3 |
162 |
lower_val |
55106 |
1 |
|
|
T1 |
126 |
|
T2 |
86 |
|
T3 |
188 |
zero_val |
6 |
1 |
|
|
T154 |
2 |
|
T155 |
2 |
|
T156 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6072 |
1 |
|
|
T1 |
14 |
|
T3 |
54 |
|
T12 |
45 |
higher_val |
higher_val |
auto[1] |
7741 |
1 |
|
|
T1 |
17 |
|
T2 |
23 |
|
T12 |
33 |
higher_val |
lower_val |
auto[0] |
5997 |
1 |
|
|
T1 |
11 |
|
T3 |
61 |
|
T12 |
40 |
higher_val |
lower_val |
auto[1] |
7628 |
1 |
|
|
T1 |
13 |
|
T2 |
28 |
|
T12 |
39 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T154 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
6139 |
1 |
|
|
T1 |
10 |
|
T3 |
37 |
|
T12 |
43 |
lower_val |
higher_val |
auto[1] |
7648 |
1 |
|
|
T1 |
25 |
|
T2 |
23 |
|
T12 |
57 |
lower_val |
lower_val |
auto[0] |
6014 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
43 |
lower_val |
lower_val |
auto[1] |
7624 |
1 |
|
|
T1 |
17 |
|
T2 |
20 |
|
T12 |
43 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T155 |
1 |
|
T156 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T154 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
321 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
72 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T22 |
1 |
zero_val |
lower_val |
auto[0] |
329 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
83 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T22 |
1 |