Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16218456	1			T1	9246		T2	1262		T3	1832
all_pins[1]	16218456	1			T1	9246		T2	1262		T3	1832
all_pins[2]	16218456	1			T1	9246		T2	1262		T3	1832

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48339928	1			T1	27583		T2	3654		T3	5223
values[0x1]	315440	1			T1	155		T2	132		T3	273
transitions[0x0=>0x1]	313983	1			T1	155		T2	132		T3	273
transitions[0x1=>0x0]	314013	1			T1	155		T2	132		T3	273

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16146896	1			T1	9091		T2	1130		T3	1559
all_pins[0]	values[0x1]	71560	1			T1	155		T2	132		T3	273
all_pins[0]	transitions[0x0=>0x1]	71548	1			T1	155		T2	132		T3	273
all_pins[0]	transitions[0x1=>0x0]	75	1			T170	2		T171	8		T172	3
all_pins[1]	values[0x0]	16218369	1			T1	9246		T2	1262		T3	1832
all_pins[1]	values[0x1]	87	1			T170	2		T171	8		T172	3
all_pins[1]	transitions[0x0=>0x1]	66	1			T170	2		T171	8		T172	3
all_pins[1]	transitions[0x1=>0x0]	243772	1			T21	15320		T22	2448		T27	1010
all_pins[2]	values[0x0]	15974663	1			T1	9246		T2	1262		T3	1832
all_pins[2]	values[0x1]	243793	1			T21	15320		T22	2448		T27	1010
all_pins[2]	transitions[0x0=>0x1]	242369	1			T21	15211		T22	2434		T27	1010
all_pins[2]	transitions[0x1=>0x0]	70166	1			T1	155		T2	132		T3	273