Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6202389 |
1 |
|
|
T1 |
11543 |
|
T2 |
13484 |
|
T3 |
6585 |
auto[1] |
9506508 |
1 |
|
|
T1 |
18202 |
|
T2 |
19798 |
|
T3 |
11992 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15675925 |
1 |
|
|
T1 |
29672 |
|
T2 |
33218 |
|
T3 |
18460 |
triple_byte_access |
10909 |
1 |
|
|
T1 |
25 |
|
T2 |
21 |
|
T3 |
34 |
halfword_access |
11010 |
1 |
|
|
T1 |
27 |
|
T2 |
30 |
|
T3 |
41 |
byte_access |
11053 |
1 |
|
|
T1 |
21 |
|
T2 |
13 |
|
T3 |
42 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6169417 |
1 |
|
|
T1 |
11470 |
|
T2 |
13420 |
|
T3 |
6468 |
auto[0] |
triple_byte_access |
10909 |
1 |
|
|
T1 |
25 |
|
T2 |
21 |
|
T3 |
34 |
auto[0] |
halfword_access |
11010 |
1 |
|
|
T1 |
27 |
|
T2 |
30 |
|
T3 |
41 |
auto[0] |
byte_access |
11053 |
1 |
|
|
T1 |
21 |
|
T2 |
13 |
|
T3 |
42 |
auto[1] |
word_access |
9506508 |
1 |
|
|
T1 |
18202 |
|
T2 |
19798 |
|
T3 |
11992 |