Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.88 95.77 90.51 100.00 67.77 93.67 98.84 96.58


Total test records in report: 872
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T768 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2954041348 Aug 15 06:12:42 PM PDT 24 Aug 15 06:12:43 PM PDT 24 20280972 ps
T769 /workspace/coverage/cover_reg_top/2.kmac_intr_test.3403718096 Aug 15 06:12:41 PM PDT 24 Aug 15 06:12:42 PM PDT 24 44205122 ps
T770 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1375910636 Aug 15 06:12:49 PM PDT 24 Aug 15 06:12:51 PM PDT 24 136249722 ps
T771 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3532450836 Aug 15 06:13:00 PM PDT 24 Aug 15 06:13:01 PM PDT 24 57677155 ps
T772 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.4010554589 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:03 PM PDT 24 80103990 ps
T773 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3115848394 Aug 15 06:12:42 PM PDT 24 Aug 15 06:12:43 PM PDT 24 16498425 ps
T774 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2882399531 Aug 15 06:12:42 PM PDT 24 Aug 15 06:12:43 PM PDT 24 13432464 ps
T775 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4025904344 Aug 15 06:12:50 PM PDT 24 Aug 15 06:12:54 PM PDT 24 115453597 ps
T776 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.733268327 Aug 15 06:12:49 PM PDT 24 Aug 15 06:12:50 PM PDT 24 32627008 ps
T777 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1034240898 Aug 15 06:12:38 PM PDT 24 Aug 15 06:12:39 PM PDT 24 30427250 ps
T778 /workspace/coverage/cover_reg_top/17.kmac_intr_test.2080478877 Aug 15 06:13:03 PM PDT 24 Aug 15 06:13:04 PM PDT 24 16864291 ps
T779 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.739931700 Aug 15 06:12:49 PM PDT 24 Aug 15 06:12:51 PM PDT 24 66935305 ps
T780 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3694070630 Aug 15 06:13:02 PM PDT 24 Aug 15 06:13:04 PM PDT 24 208195013 ps
T120 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2902213975 Aug 15 06:12:37 PM PDT 24 Aug 15 06:12:40 PM PDT 24 132738879 ps
T781 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3998884738 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:48 PM PDT 24 46681978 ps
T782 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2140192491 Aug 15 06:12:39 PM PDT 24 Aug 15 06:12:58 PM PDT 24 990703884 ps
T139 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2300848417 Aug 15 06:12:43 PM PDT 24 Aug 15 06:12:45 PM PDT 24 167652086 ps
T783 /workspace/coverage/cover_reg_top/13.kmac_intr_test.529821080 Aug 15 06:12:50 PM PDT 24 Aug 15 06:12:52 PM PDT 24 98387675 ps
T784 /workspace/coverage/cover_reg_top/47.kmac_intr_test.1074207794 Aug 15 06:13:07 PM PDT 24 Aug 15 06:13:08 PM PDT 24 16064759 ps
T785 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3499490162 Aug 15 06:12:43 PM PDT 24 Aug 15 06:12:44 PM PDT 24 71843769 ps
T786 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2001304626 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:48 PM PDT 24 136348387 ps
T787 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1216644758 Aug 15 06:13:02 PM PDT 24 Aug 15 06:13:03 PM PDT 24 12682213 ps
T788 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1294582340 Aug 15 06:12:56 PM PDT 24 Aug 15 06:13:00 PM PDT 24 665775801 ps
T789 /workspace/coverage/cover_reg_top/31.kmac_intr_test.386886233 Aug 15 06:13:03 PM PDT 24 Aug 15 06:13:05 PM PDT 24 56054488 ps
T790 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1353488738 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:50 PM PDT 24 367181506 ps
T791 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1193843816 Aug 15 06:12:48 PM PDT 24 Aug 15 06:12:51 PM PDT 24 47048377 ps
T121 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2933040006 Aug 15 06:12:57 PM PDT 24 Aug 15 06:13:00 PM PDT 24 165732105 ps
T140 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3818670879 Aug 15 06:12:41 PM PDT 24 Aug 15 06:12:42 PM PDT 24 41071182 ps
T792 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1988110773 Aug 15 06:12:33 PM PDT 24 Aug 15 06:12:43 PM PDT 24 2246880804 ps
T793 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2380750828 Aug 15 06:12:40 PM PDT 24 Aug 15 06:12:43 PM PDT 24 140813917 ps
T174 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1533540251 Aug 15 06:12:51 PM PDT 24 Aug 15 06:12:56 PM PDT 24 427408244 ps
T794 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.592882974 Aug 15 06:12:40 PM PDT 24 Aug 15 06:12:42 PM PDT 24 387560871 ps
T795 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2361815873 Aug 15 06:12:42 PM PDT 24 Aug 15 06:12:45 PM PDT 24 101125690 ps
T122 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3301516592 Aug 15 06:12:51 PM PDT 24 Aug 15 06:12:53 PM PDT 24 64832986 ps
T796 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1161478574 Aug 15 06:13:14 PM PDT 24 Aug 15 06:13:17 PM PDT 24 155310988 ps
T797 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.602338155 Aug 15 06:12:51 PM PDT 24 Aug 15 06:12:52 PM PDT 24 88075114 ps
T798 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3421622057 Aug 15 06:12:26 PM PDT 24 Aug 15 06:12:27 PM PDT 24 134839962 ps
T799 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.18207665 Aug 15 06:12:55 PM PDT 24 Aug 15 06:12:56 PM PDT 24 30913419 ps
T800 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.220234292 Aug 15 06:13:02 PM PDT 24 Aug 15 06:13:04 PM PDT 24 165077358 ps
T116 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1385316028 Aug 15 06:13:21 PM PDT 24 Aug 15 06:13:23 PM PDT 24 246303840 ps
T801 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1985339378 Aug 15 06:13:31 PM PDT 24 Aug 15 06:13:34 PM PDT 24 198410777 ps
T802 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3281734281 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:04 PM PDT 24 117976910 ps
T803 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1733155995 Aug 15 06:13:03 PM PDT 24 Aug 15 06:13:06 PM PDT 24 48188632 ps
T804 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2262462678 Aug 15 06:12:37 PM PDT 24 Aug 15 06:12:38 PM PDT 24 99109526 ps
T125 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2098186499 Aug 15 06:13:49 PM PDT 24 Aug 15 06:13:52 PM PDT 24 90507938 ps
T127 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.410263255 Aug 15 06:12:54 PM PDT 24 Aug 15 06:12:57 PM PDT 24 126451522 ps
T805 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3721680586 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:49 PM PDT 24 168112724 ps
T124 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.277019095 Aug 15 06:13:14 PM PDT 24 Aug 15 06:13:17 PM PDT 24 186297417 ps
T806 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3983378416 Aug 15 06:13:03 PM PDT 24 Aug 15 06:13:04 PM PDT 24 117650643 ps
T807 /workspace/coverage/cover_reg_top/34.kmac_intr_test.3614179139 Aug 15 06:13:07 PM PDT 24 Aug 15 06:13:08 PM PDT 24 22756454 ps
T808 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4246648303 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:50 PM PDT 24 152076864 ps
T809 /workspace/coverage/cover_reg_top/5.kmac_intr_test.3707187168 Aug 15 06:12:40 PM PDT 24 Aug 15 06:12:41 PM PDT 24 15607259 ps
T810 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2056388551 Aug 15 06:12:33 PM PDT 24 Aug 15 06:12:36 PM PDT 24 227872275 ps
T811 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3311164421 Aug 15 06:12:54 PM PDT 24 Aug 15 06:12:57 PM PDT 24 104124743 ps
T812 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3164208259 Aug 15 06:12:53 PM PDT 24 Aug 15 06:12:54 PM PDT 24 77401770 ps
T128 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.185224841 Aug 15 06:12:56 PM PDT 24 Aug 15 06:12:57 PM PDT 24 29289142 ps
T123 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.4069522556 Aug 15 06:12:48 PM PDT 24 Aug 15 06:12:51 PM PDT 24 188694379 ps
T813 /workspace/coverage/cover_reg_top/9.kmac_intr_test.1609433923 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:02 PM PDT 24 47124703 ps
T814 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1762775984 Aug 15 06:12:48 PM PDT 24 Aug 15 06:12:52 PM PDT 24 147834723 ps
T815 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3539516569 Aug 15 06:13:02 PM PDT 24 Aug 15 06:13:05 PM PDT 24 137618644 ps
T816 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2186555263 Aug 15 06:12:52 PM PDT 24 Aug 15 06:12:54 PM PDT 24 69007323 ps
T817 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1446574467 Aug 15 06:12:38 PM PDT 24 Aug 15 06:12:41 PM PDT 24 297524783 ps
T818 /workspace/coverage/cover_reg_top/38.kmac_intr_test.1926382922 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:02 PM PDT 24 49668633 ps
T819 /workspace/coverage/cover_reg_top/36.kmac_intr_test.1300928304 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:02 PM PDT 24 45535460 ps
T820 /workspace/coverage/cover_reg_top/35.kmac_intr_test.1892709912 Aug 15 06:13:06 PM PDT 24 Aug 15 06:13:07 PM PDT 24 11493728 ps
T821 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.756823662 Aug 15 06:12:58 PM PDT 24 Aug 15 06:13:00 PM PDT 24 80939569 ps
T822 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3495143119 Aug 15 06:12:46 PM PDT 24 Aug 15 06:12:48 PM PDT 24 54842163 ps
T823 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1281146148 Aug 15 06:12:48 PM PDT 24 Aug 15 06:12:50 PM PDT 24 76355268 ps
T129 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2170181210 Aug 15 06:12:44 PM PDT 24 Aug 15 06:12:47 PM PDT 24 92288435 ps
T824 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3806670210 Aug 15 06:12:56 PM PDT 24 Aug 15 06:12:57 PM PDT 24 97145141 ps
T126 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2240777171 Aug 15 06:12:56 PM PDT 24 Aug 15 06:12:59 PM PDT 24 234546033 ps
T825 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1506779231 Aug 15 06:13:02 PM PDT 24 Aug 15 06:13:04 PM PDT 24 115947943 ps
T826 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1495319260 Aug 15 06:12:34 PM PDT 24 Aug 15 06:12:36 PM PDT 24 44771309 ps
T827 /workspace/coverage/cover_reg_top/11.kmac_intr_test.3200436341 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:53 PM PDT 24 13772370 ps
T828 /workspace/coverage/cover_reg_top/16.kmac_intr_test.2466490999 Aug 15 06:12:56 PM PDT 24 Aug 15 06:12:57 PM PDT 24 56643985 ps
T829 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2790226758 Aug 15 06:13:08 PM PDT 24 Aug 15 06:13:12 PM PDT 24 159430849 ps
T830 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.4203209418 Aug 15 06:12:49 PM PDT 24 Aug 15 06:12:51 PM PDT 24 146508978 ps
T831 /workspace/coverage/cover_reg_top/29.kmac_intr_test.4275567909 Aug 15 06:13:02 PM PDT 24 Aug 15 06:13:13 PM PDT 24 37224254 ps
T832 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.679902734 Aug 15 06:13:00 PM PDT 24 Aug 15 06:13:03 PM PDT 24 493112787 ps
T833 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1211823786 Aug 15 06:12:35 PM PDT 24 Aug 15 06:12:36 PM PDT 24 45647243 ps
T834 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.108078439 Aug 15 06:12:58 PM PDT 24 Aug 15 06:13:00 PM PDT 24 123702596 ps
T835 /workspace/coverage/cover_reg_top/32.kmac_intr_test.61376376 Aug 15 06:13:11 PM PDT 24 Aug 15 06:13:11 PM PDT 24 158802358 ps
T836 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2622358609 Aug 15 06:12:35 PM PDT 24 Aug 15 06:12:38 PM PDT 24 142555673 ps
T837 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1535988382 Aug 15 06:12:49 PM PDT 24 Aug 15 06:12:52 PM PDT 24 153393140 ps
T838 /workspace/coverage/cover_reg_top/10.kmac_intr_test.412559324 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:48 PM PDT 24 14136395 ps
T839 /workspace/coverage/cover_reg_top/18.kmac_intr_test.2885484105 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:02 PM PDT 24 15482764 ps
T840 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3807081560 Aug 15 06:12:40 PM PDT 24 Aug 15 06:12:42 PM PDT 24 49309777 ps
T841 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2960673597 Aug 15 06:13:12 PM PDT 24 Aug 15 06:13:15 PM PDT 24 443703469 ps
T842 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3437883109 Aug 15 06:12:53 PM PDT 24 Aug 15 06:12:57 PM PDT 24 120593207 ps
T843 /workspace/coverage/cover_reg_top/42.kmac_intr_test.3058889850 Aug 15 06:12:59 PM PDT 24 Aug 15 06:13:05 PM PDT 24 41293000 ps
T844 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1697372526 Aug 15 06:12:34 PM PDT 24 Aug 15 06:12:36 PM PDT 24 292337597 ps
T845 /workspace/coverage/cover_reg_top/26.kmac_intr_test.899537067 Aug 15 06:13:09 PM PDT 24 Aug 15 06:13:10 PM PDT 24 22065411 ps
T175 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.601084352 Aug 15 06:12:37 PM PDT 24 Aug 15 06:12:40 PM PDT 24 237811898 ps
T141 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.353912435 Aug 15 06:12:33 PM PDT 24 Aug 15 06:12:34 PM PDT 24 176742531 ps
T846 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.44894763 Aug 15 06:13:07 PM PDT 24 Aug 15 06:13:08 PM PDT 24 92056532 ps
T847 /workspace/coverage/cover_reg_top/30.kmac_intr_test.3571961047 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:02 PM PDT 24 30484304 ps
T848 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2189158968 Aug 15 06:14:06 PM PDT 24 Aug 15 06:14:07 PM PDT 24 61703455 ps
T849 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1477661507 Aug 15 06:13:03 PM PDT 24 Aug 15 06:13:05 PM PDT 24 37900478 ps
T850 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1844092859 Aug 15 06:13:10 PM PDT 24 Aug 15 06:13:13 PM PDT 24 120428022 ps
T851 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2024543712 Aug 15 06:12:54 PM PDT 24 Aug 15 06:12:56 PM PDT 24 46154635 ps
T852 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.4167758524 Aug 15 06:12:47 PM PDT 24 Aug 15 06:12:48 PM PDT 24 39636875 ps
T853 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2432666433 Aug 15 06:12:52 PM PDT 24 Aug 15 06:12:53 PM PDT 24 63107512 ps
T854 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.4225077093 Aug 15 06:12:32 PM PDT 24 Aug 15 06:12:35 PM PDT 24 364218969 ps
T855 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.56140344 Aug 15 06:12:41 PM PDT 24 Aug 15 06:12:44 PM PDT 24 154763071 ps
T856 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3890889975 Aug 15 06:12:34 PM PDT 24 Aug 15 06:12:42 PM PDT 24 299319946 ps
T857 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.501325056 Aug 15 06:13:46 PM PDT 24 Aug 15 06:13:53 PM PDT 24 278384539 ps
T858 /workspace/coverage/cover_reg_top/0.kmac_intr_test.249223064 Aug 15 06:12:46 PM PDT 24 Aug 15 06:12:47 PM PDT 24 42471852 ps
T859 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1309071687 Aug 15 06:12:46 PM PDT 24 Aug 15 06:12:48 PM PDT 24 39576916 ps
T860 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3448313673 Aug 15 06:12:32 PM PDT 24 Aug 15 06:12:35 PM PDT 24 521941573 ps
T861 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.660607140 Aug 15 06:12:36 PM PDT 24 Aug 15 06:12:37 PM PDT 24 15519923 ps
T862 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.556803846 Aug 15 06:12:39 PM PDT 24 Aug 15 06:12:51 PM PDT 24 6090252202 ps
T863 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3039707237 Aug 15 06:12:53 PM PDT 24 Aug 15 06:12:54 PM PDT 24 75282372 ps
T864 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2308135580 Aug 15 06:12:39 PM PDT 24 Aug 15 06:12:41 PM PDT 24 22454013 ps
T865 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2495138496 Aug 15 06:13:01 PM PDT 24 Aug 15 06:13:07 PM PDT 24 42283890 ps
T866 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.4131625815 Aug 15 06:12:49 PM PDT 24 Aug 15 06:12:50 PM PDT 24 21614171 ps
T867 /workspace/coverage/cover_reg_top/43.kmac_intr_test.4137047734 Aug 15 06:13:02 PM PDT 24 Aug 15 06:13:03 PM PDT 24 42615289 ps
T868 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4254898167 Aug 15 06:13:10 PM PDT 24 Aug 15 06:13:12 PM PDT 24 171824857 ps
T869 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2118265991 Aug 15 06:12:53 PM PDT 24 Aug 15 06:12:54 PM PDT 24 17637751 ps
T870 /workspace/coverage/cover_reg_top/6.kmac_intr_test.1907852966 Aug 15 06:12:44 PM PDT 24 Aug 15 06:12:45 PM PDT 24 18085531 ps
T871 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1722470698 Aug 15 06:12:35 PM PDT 24 Aug 15 06:12:37 PM PDT 24 202691428 ps
T173 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3768724263 Aug 15 06:12:39 PM PDT 24 Aug 15 06:12:42 PM PDT 24 210355563 ps
T872 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2147372121 Aug 15 06:12:52 PM PDT 24 Aug 15 06:12:54 PM PDT 24 151173483 ps

Test location /workspace/coverage/default/34.kmac_entropy_refresh.309663184
Short name T13
Test name
Test status
Simulation time 13143479622 ps
CPU time 271.32 seconds
Started Aug 15 05:56:49 PM PDT 24
Finished Aug 15 06:01:21 PM PDT 24
Peak memory 461296 kb
Host smart-260a24fc-6500-404f-9ca0-09d1156cd4e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309663184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.30
9663184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.859981356
Short name T47
Test name
Test status
Simulation time 479540398 ps
CPU time 2.95 seconds
Started Aug 15 06:12:55 PM PDT 24
Finished Aug 15 06:12:58 PM PDT 24
Peak memory 207048 kb
Host smart-db53227d-d456-46df-b17b-9b1299197fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859981356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.85998
1356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.955052749
Short name T6
Test name
Test status
Simulation time 18599202471 ps
CPU time 67.83 seconds
Started Aug 15 05:55:46 PM PDT 24
Finished Aug 15 05:56:54 PM PDT 24
Peak memory 267032 kb
Host smart-af542c31-36c6-4970-91d1-5ba524864e43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955052749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.955052749 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/16.kmac_key_error.4123664190
Short name T19
Test name
Test status
Simulation time 1389418811 ps
CPU time 7.39 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 217576 kb
Host smart-96986f58-2388-403d-8ab6-43cab45507f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123664190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.4123664190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_error.1642790668
Short name T27
Test name
Test status
Simulation time 88047092777 ps
CPU time 457.4 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 06:04:39 PM PDT 24
Peak memory 616028 kb
Host smart-2c4f211e-bcf6-40f4-bb14-bc66a1dc0018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642790668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1642790668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.4284520719
Short name T5
Test name
Test status
Simulation time 87384663 ps
CPU time 1.3 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 05:56:50 PM PDT 24
Peak memory 223276 kb
Host smart-3b8c3610-aa5d-486f-af4c-e012f5e17205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284520719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4284520719 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3854569380
Short name T113
Test name
Test status
Simulation time 54056902 ps
CPU time 3.35 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:38 PM PDT 24
Peak memory 223260 kb
Host smart-a79ad096-d695-4cba-9302-7eb6cb17137e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854569380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3854569380 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1207329862
Short name T2
Test name
Test status
Simulation time 7356943183 ps
CPU time 337.74 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 06:01:44 PM PDT 24
Peak memory 232632 kb
Host smart-ca1ec4e7-2a1c-45a1-a51a-7c7328ceac65
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207329862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.120732986
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1562931128
Short name T97
Test name
Test status
Simulation time 27534775 ps
CPU time 1.09 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 215340 kb
Host smart-f3d92032-baf9-48a6-aff5-da96944f8509
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562931128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.1562931128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.1422223456
Short name T34
Test name
Test status
Simulation time 93061870 ps
CPU time 1.14 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:57:14 PM PDT 24
Peak memory 219112 kb
Host smart-2b3bad76-a8ac-4d24-89e8-14b7e110e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422223456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1422223456 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1975408833
Short name T163
Test name
Test status
Simulation time 14056651 ps
CPU time 0.87 seconds
Started Aug 15 06:12:36 PM PDT 24
Finished Aug 15 06:12:37 PM PDT 24
Peak memory 206428 kb
Host smart-838a521e-f5ea-4417-837a-27d5ef6eb404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975408833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1975408833 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.3166616673
Short name T52
Test name
Test status
Simulation time 4740405345 ps
CPU time 19.54 seconds
Started Aug 15 05:56:29 PM PDT 24
Finished Aug 15 05:56:49 PM PDT 24
Peak memory 248464 kb
Host smart-b7314511-0d56-4df6-ae5d-4907f137b54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166616673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3166616673 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.970326007
Short name T53
Test name
Test status
Simulation time 107543383 ps
CPU time 1.32 seconds
Started Aug 15 05:56:13 PM PDT 24
Finished Aug 15 05:56:14 PM PDT 24
Peak memory 218936 kb
Host smart-21f97995-8b09-4ee0-a121-95597bf4e464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970326007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.970326007 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_stress_all.1459081707
Short name T50
Test name
Test status
Simulation time 50718498303 ps
CPU time 1128.91 seconds
Started Aug 15 05:55:52 PM PDT 24
Finished Aug 15 06:14:41 PM PDT 24
Peak memory 631452 kb
Host smart-7a091dda-07ae-4295-b29d-8acb412891d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1459081707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1459081707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3572707783
Short name T1
Test name
Test status
Simulation time 38022378484 ps
CPU time 173.83 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:59:13 PM PDT 24
Peak memory 314892 kb
Host smart-a20eff7a-363c-4765-8c04-be8159cf935e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3572707783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3572707783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2712202803
Short name T198
Test name
Test status
Simulation time 47600296 ps
CPU time 0.78 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 05:56:02 PM PDT 24
Peak memory 204864 kb
Host smart-335c9256-d1ae-4af0-9310-60690109f42d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712202803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2712202803 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1677291512
Short name T137
Test name
Test status
Simulation time 44839444 ps
CPU time 1.44 seconds
Started Aug 15 06:12:38 PM PDT 24
Finished Aug 15 06:12:40 PM PDT 24
Peak memory 214892 kb
Host smart-761afbd9-3c93-4332-9265-78c4c28d508f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677291512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.1677291512 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.154598396
Short name T35
Test name
Test status
Simulation time 97267034 ps
CPU time 1.37 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:16 PM PDT 24
Peak memory 218968 kb
Host smart-fda136bc-e509-46db-aa65-0a6bf5c3b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154598396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.154598396 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.4069522556
Short name T123
Test name
Test status
Simulation time 188694379 ps
CPU time 3.13 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215020 kb
Host smart-e7fd9cf6-d211-49ca-8523-943b1c1f6e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069522556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4069522556 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4025904344
Short name T775
Test name
Test status
Simulation time 115453597 ps
CPU time 2.87 seconds
Started Aug 15 06:12:50 PM PDT 24
Finished Aug 15 06:12:54 PM PDT 24
Peak memory 223556 kb
Host smart-fee9148f-52ff-4159-b58a-e0fedfc24adb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025904344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.4025904344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.4091911466
Short name T136
Test name
Test status
Simulation time 794929843 ps
CPU time 3.8 seconds
Started Aug 15 06:12:49 PM PDT 24
Finished Aug 15 06:12:53 PM PDT 24
Peak memory 217932 kb
Host smart-d9f44674-ac14-4974-b471-06500e5d7c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091911466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.40919
11466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2571293186
Short name T104
Test name
Test status
Simulation time 3779227644 ps
CPU time 98.3 seconds
Started Aug 15 05:56:53 PM PDT 24
Finished Aug 15 05:58:32 PM PDT 24
Peak memory 261016 kb
Host smart-08be116d-dfd3-4d06-8ab4-80837eb6bbd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571293186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2
571293186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.118792572
Short name T164
Test name
Test status
Simulation time 12142799 ps
CPU time 0.72 seconds
Started Aug 15 06:13:50 PM PDT 24
Finished Aug 15 06:13:51 PM PDT 24
Peak memory 206488 kb
Host smart-bbc9c534-9775-4d59-82b7-fdf575791aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118792572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.118792572 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/default/39.kmac_app.1319551359
Short name T154
Test name
Test status
Simulation time 5833429477 ps
CPU time 102.83 seconds
Started Aug 15 05:57:00 PM PDT 24
Finished Aug 15 05:58:43 PM PDT 24
Peak memory 309852 kb
Host smart-b234369c-c55b-40e2-9c55-80de76e8679b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319551359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1319551359 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_stress_all.394504381
Short name T39
Test name
Test status
Simulation time 37102334719 ps
CPU time 1240.26 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 06:16:56 PM PDT 24
Peak memory 575052 kb
Host smart-55bf2474-fc54-44b2-a896-70aa74743823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=394504381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.394504381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1193843816
Short name T791
Test name
Test status
Simulation time 47048377 ps
CPU time 2.37 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215356 kb
Host smart-b49b4847-70fe-4776-87b7-2bd5435878ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193843816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.1193843816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1760144698
Short name T145
Test name
Test status
Simulation time 119259390 ps
CPU time 4.13 seconds
Started Aug 15 06:12:44 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 217572 kb
Host smart-db261231-ce07-421e-9889-ca5f1b84d4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760144698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.17601
44698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3326797079
Short name T12
Test name
Test status
Simulation time 272208240797 ps
CPU time 2532.93 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 06:39:22 PM PDT 24
Peak memory 2351516 kb
Host smart-7c2bf6fb-dfc5-4242-b0ef-6d898479ddac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3326797079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3326797079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1048581167
Short name T42
Test name
Test status
Simulation time 107690521200 ps
CPU time 76.4 seconds
Started Aug 15 05:55:44 PM PDT 24
Finished Aug 15 05:57:01 PM PDT 24
Peak memory 218812 kb
Host smart-9dcfe46a-6f11-4b5c-96b0-298232aa8db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048581167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1048581167 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/24.kmac_error.2154361956
Short name T306
Test name
Test status
Simulation time 67784826626 ps
CPU time 396.87 seconds
Started Aug 15 05:56:29 PM PDT 24
Finished Aug 15 06:03:06 PM PDT 24
Peak memory 595416 kb
Host smart-424b8bec-d6e9-4243-bc65-909a69bad9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154361956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2154361956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.277019095
Short name T124
Test name
Test status
Simulation time 186297417 ps
CPU time 3.25 seconds
Started Aug 15 06:13:14 PM PDT 24
Finished Aug 15 06:13:17 PM PDT 24
Peak memory 215000 kb
Host smart-0936fa61-a9a3-4e02-ae71-1be72a854e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277019095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.277019095 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.3429523260
Short name T117
Test name
Test status
Simulation time 14144289 ps
CPU time 0.75 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 206460 kb
Host smart-a81e1ccd-1228-4870-be98-34e22415a754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429523260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3429523260 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.584010259
Short name T156
Test name
Test status
Simulation time 144416554944 ps
CPU time 1775.36 seconds
Started Aug 15 05:56:12 PM PDT 24
Finished Aug 15 06:25:48 PM PDT 24
Peak memory 1150660 kb
Host smart-d1b81852-6473-47fe-9b1f-66bd79d4717a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=584010259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.584010259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.185224841
Short name T128
Test name
Test status
Simulation time 29289142 ps
CPU time 1.74 seconds
Started Aug 15 06:12:56 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 217964 kb
Host smart-1757c2d0-fc1b-42cb-8889-ab0edd168ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185224841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.185224841 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/default/15.kmac_error.1554951559
Short name T467
Test name
Test status
Simulation time 3419877571 ps
CPU time 279.07 seconds
Started Aug 15 05:56:26 PM PDT 24
Finished Aug 15 06:01:06 PM PDT 24
Peak memory 339356 kb
Host smart-54f5aac6-b164-4114-9564-beaadb7fec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554951559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1554951559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1988110773
Short name T792
Test name
Test status
Simulation time 2246880804 ps
CPU time 9.6 seconds
Started Aug 15 06:12:33 PM PDT 24
Finished Aug 15 06:12:43 PM PDT 24
Peak memory 206732 kb
Host smart-ef93d6c7-07c3-4031-925e-ef161fffe701
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988110773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1988110
773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2140192491
Short name T782
Test name
Test status
Simulation time 990703884 ps
CPU time 17.97 seconds
Started Aug 15 06:12:39 PM PDT 24
Finished Aug 15 06:12:58 PM PDT 24
Peak memory 206728 kb
Host smart-5d7dd19c-4f46-4e30-ae32-6fb640fcf083
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140192491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2140192
491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2305493537
Short name T744
Test name
Test status
Simulation time 22977118 ps
CPU time 0.95 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 206412 kb
Host smart-ec553d39-4dcf-425d-bd51-99df60e3a709
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305493537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2305493
537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3448313673
Short name T860
Test name
Test status
Simulation time 521941573 ps
CPU time 2.49 seconds
Started Aug 15 06:12:32 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 223200 kb
Host smart-05c5f6a7-6749-4d4f-8929-5f8073ee3d4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448313673 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3448313673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.942105176
Short name T747
Test name
Test status
Simulation time 113684713 ps
CPU time 1.13 seconds
Started Aug 15 06:12:33 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 206816 kb
Host smart-5788dfda-4e4e-461b-ab82-5e5b4e4baec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942105176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.942105176 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.249223064
Short name T858
Test name
Test status
Simulation time 42471852 ps
CPU time 0.77 seconds
Started Aug 15 06:12:46 PM PDT 24
Finished Aug 15 06:12:47 PM PDT 24
Peak memory 206460 kb
Host smart-e3ef9238-8463-4705-a8c7-c37ec61ab809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249223064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.249223064 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3467393657
Short name T734
Test name
Test status
Simulation time 37775958 ps
CPU time 0.71 seconds
Started Aug 15 06:12:38 PM PDT 24
Finished Aug 15 06:12:39 PM PDT 24
Peak memory 206468 kb
Host smart-87ce43d4-4549-4302-8b85-7b13bcb009cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467393657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3467393657
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.4225077093
Short name T854
Test name
Test status
Simulation time 364218969 ps
CPU time 2.56 seconds
Started Aug 15 06:12:32 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 214924 kb
Host smart-91b88f7b-ec91-4a4d-ad59-02a21408186d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225077093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.4225077093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1722470698
Short name T871
Test name
Test status
Simulation time 202691428 ps
CPU time 1.12 seconds
Started Aug 15 06:12:35 PM PDT 24
Finished Aug 15 06:12:37 PM PDT 24
Peak memory 215516 kb
Host smart-45328bcf-fd76-4cd7-8f40-d4917a40e14d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722470698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.1722470698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2262462678
Short name T804
Test name
Test status
Simulation time 99109526 ps
CPU time 1.69 seconds
Started Aug 15 06:12:37 PM PDT 24
Finished Aug 15 06:12:38 PM PDT 24
Peak memory 215496 kb
Host smart-3d297bd4-e753-4a5b-add4-bbb5fb7195ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262462678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2262462678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2622358609
Short name T836
Test name
Test status
Simulation time 142555673 ps
CPU time 3.29 seconds
Started Aug 15 06:12:35 PM PDT 24
Finished Aug 15 06:12:38 PM PDT 24
Peak memory 214980 kb
Host smart-fe93b83e-7d34-4342-ae45-6ffec2cc41bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622358609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2622358609 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3768724263
Short name T173
Test name
Test status
Simulation time 210355563 ps
CPU time 2.77 seconds
Started Aug 15 06:12:39 PM PDT 24
Finished Aug 15 06:12:42 PM PDT 24
Peak memory 207116 kb
Host smart-77c50f50-3277-4e1d-af94-00c1ff6cda8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768724263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.37687
24263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2661156864
Short name T732
Test name
Test status
Simulation time 133569994 ps
CPU time 4.13 seconds
Started Aug 15 06:12:27 PM PDT 24
Finished Aug 15 06:12:32 PM PDT 24
Peak memory 206720 kb
Host smart-abae85f7-15aa-4560-919c-29eb971f8cf8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661156864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2661156
864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3890889975
Short name T856
Test name
Test status
Simulation time 299319946 ps
CPU time 7.86 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:42 PM PDT 24
Peak memory 206768 kb
Host smart-1885b0ad-ae3c-4c30-968c-fc123e4db710
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890889975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3890889
975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1495319260
Short name T826
Test name
Test status
Simulation time 44771309 ps
CPU time 1.1 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:36 PM PDT 24
Peak memory 214892 kb
Host smart-5719fea2-64a4-467c-a800-6e54f8b4787e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495319260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1495319
260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1697372526
Short name T844
Test name
Test status
Simulation time 292337597 ps
CPU time 2.29 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:36 PM PDT 24
Peak memory 216472 kb
Host smart-b9ea9167-7dcb-4526-a667-224fa7a5d9dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697372526 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1697372526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3115848394
Short name T773
Test name
Test status
Simulation time 16498425 ps
CPU time 0.94 seconds
Started Aug 15 06:12:42 PM PDT 24
Finished Aug 15 06:12:43 PM PDT 24
Peak memory 206480 kb
Host smart-81d698e0-a963-4a3b-bbcd-00893ec46a69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115848394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3115848394 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.557659927
Short name T762
Test name
Test status
Simulation time 39042754 ps
CPU time 0.78 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 206428 kb
Host smart-9e0ca427-d589-4b54-bec3-df0c4a5e5c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557659927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.557659927 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.353912435
Short name T141
Test name
Test status
Simulation time 176742531 ps
CPU time 1.33 seconds
Started Aug 15 06:12:33 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 214896 kb
Host smart-893fe386-692e-47fa-abed-05d4718b13c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353912435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial
_access.353912435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.660607140
Short name T861
Test name
Test status
Simulation time 15519923 ps
CPU time 0.73 seconds
Started Aug 15 06:12:36 PM PDT 24
Finished Aug 15 06:12:37 PM PDT 24
Peak memory 206520 kb
Host smart-86d60f67-ec66-4b0a-9c7a-3a323613f227
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660607140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.660607140 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1800600622
Short name T147
Test name
Test status
Simulation time 88074730 ps
CPU time 2.23 seconds
Started Aug 15 06:12:33 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 214968 kb
Host smart-edbda580-459b-4746-8029-f17f5ac3ee31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800600622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.1800600622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3473473493
Short name T100
Test name
Test status
Simulation time 30171472 ps
CPU time 1.04 seconds
Started Aug 15 06:12:33 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 214840 kb
Host smart-9ae97a0e-0f27-4870-a28b-76bd90293519
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473473493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3473473493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2380750828
Short name T793
Test name
Test status
Simulation time 140813917 ps
CPU time 2.85 seconds
Started Aug 15 06:12:40 PM PDT 24
Finished Aug 15 06:12:43 PM PDT 24
Peak memory 215476 kb
Host smart-58a80512-6b03-4ddb-ac71-b24d22a75536
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380750828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.2380750828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2056388551
Short name T810
Test name
Test status
Simulation time 227872275 ps
CPU time 2.65 seconds
Started Aug 15 06:12:33 PM PDT 24
Finished Aug 15 06:12:36 PM PDT 24
Peak memory 206812 kb
Host smart-28564dbb-632e-430b-b2f4-c4c997a65894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056388551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.20563
88551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1535988382
Short name T837
Test name
Test status
Simulation time 153393140 ps
CPU time 2.3 seconds
Started Aug 15 06:12:49 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 216296 kb
Host smart-b76c19c2-5695-4af9-8caa-303e1fb02dff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535988382 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1535988382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.4131625815
Short name T866
Test name
Test status
Simulation time 21614171 ps
CPU time 1.12 seconds
Started Aug 15 06:12:49 PM PDT 24
Finished Aug 15 06:12:50 PM PDT 24
Peak memory 206676 kb
Host smart-d9085cc6-a471-47fa-bd1f-c43d140fd440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131625815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.4131625815 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.412559324
Short name T838
Test name
Test status
Simulation time 14136395 ps
CPU time 0.76 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 206516 kb
Host smart-94bc66cf-8171-4965-b8a5-d02801f919f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412559324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.412559324 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3806670210
Short name T824
Test name
Test status
Simulation time 97145141 ps
CPU time 1.59 seconds
Started Aug 15 06:12:56 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 214960 kb
Host smart-dfdb97dd-1cf1-4986-ab97-57de427790d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806670210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3806670210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2001304626
Short name T786
Test name
Test status
Simulation time 136348387 ps
CPU time 1.13 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 215384 kb
Host smart-8e128a89-9165-4a40-be85-b48e79f52287
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001304626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.2001304626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.739931700
Short name T779
Test name
Test status
Simulation time 66935305 ps
CPU time 2.02 seconds
Started Aug 15 06:12:49 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215444 kb
Host smart-fd99de9a-28ab-4555-90c2-9107c143763b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739931700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac
_shadow_reg_errors_with_csr_rw.739931700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1533540251
Short name T174
Test name
Test status
Simulation time 427408244 ps
CPU time 4.66 seconds
Started Aug 15 06:12:51 PM PDT 24
Finished Aug 15 06:12:56 PM PDT 24
Peak memory 214948 kb
Host smart-715cad66-1705-4220-af58-c36e08a1c4a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533540251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1533
540251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.756823662
Short name T821
Test name
Test status
Simulation time 80939569 ps
CPU time 1.64 seconds
Started Aug 15 06:12:58 PM PDT 24
Finished Aug 15 06:13:00 PM PDT 24
Peak memory 223164 kb
Host smart-adcf2054-1dbf-4dbf-bf8d-12cc222544d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756823662 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.756823662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3243573161
Short name T764
Test name
Test status
Simulation time 14349096 ps
CPU time 0.92 seconds
Started Aug 15 06:12:50 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 206508 kb
Host smart-7b26bd87-221c-4843-a16c-49fe14f70829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243573161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3243573161 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.3200436341
Short name T827
Test name
Test status
Simulation time 13772370 ps
CPU time 0.74 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:53 PM PDT 24
Peak memory 206524 kb
Host smart-080479e7-8bd6-4a65-a5cf-2c52a6b2780d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200436341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3200436341 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3052507465
Short name T729
Test name
Test status
Simulation time 527708470 ps
CPU time 2.57 seconds
Started Aug 15 06:12:46 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 214916 kb
Host smart-fbd4f5e2-e536-4a00-a410-a3e15ae67efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052507465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3052507465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.18207665
Short name T799
Test name
Test status
Simulation time 30913419 ps
CPU time 0.9 seconds
Started Aug 15 06:12:55 PM PDT 24
Finished Aug 15 06:12:56 PM PDT 24
Peak memory 206612 kb
Host smart-90abc619-8a69-47ad-aaca-353fe70329ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18207665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_e
rrors.18207665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2186555263
Short name T816
Test name
Test status
Simulation time 69007323 ps
CPU time 1.85 seconds
Started Aug 15 06:12:52 PM PDT 24
Finished Aug 15 06:12:54 PM PDT 24
Peak memory 215484 kb
Host smart-3a8f4bda-c8e2-4f68-a49f-852097289e13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186555263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.2186555263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.410263255
Short name T127
Test name
Test status
Simulation time 126451522 ps
CPU time 2.95 seconds
Started Aug 15 06:12:54 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 215012 kb
Host smart-91ff91de-08cc-443e-aa6a-658c9f1b4239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410263255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.410263255 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.97359005
Short name T131
Test name
Test status
Simulation time 93886610 ps
CPU time 2.43 seconds
Started Aug 15 06:12:57 PM PDT 24
Finished Aug 15 06:12:59 PM PDT 24
Peak memory 214968 kb
Host smart-beba9999-b9ac-4c5b-a6e1-3ec49bf94844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97359005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.973590
05 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1281146148
Short name T823
Test name
Test status
Simulation time 76355268 ps
CPU time 1.7 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:50 PM PDT 24
Peak memory 223160 kb
Host smart-c2fb160d-07c4-499a-b1c6-5cd529ecc27b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281146148 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1281146148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1583806638
Short name T759
Test name
Test status
Simulation time 27041087 ps
CPU time 0.89 seconds
Started Aug 15 06:12:56 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 206520 kb
Host smart-2240a53f-7b5a-4d13-aeaf-219df1a377fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583806638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1583806638 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.4203209418
Short name T830
Test name
Test status
Simulation time 146508978 ps
CPU time 2.02 seconds
Started Aug 15 06:12:49 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215224 kb
Host smart-640a71a5-416d-4572-aa69-a749444e930a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203209418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.4203209418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1309071687
Short name T859
Test name
Test status
Simulation time 39576916 ps
CPU time 1.33 seconds
Started Aug 15 06:12:46 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 223480 kb
Host smart-47368bdd-9621-4a10-8ecd-83796ee0b9fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309071687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1309071687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.108078439
Short name T834
Test name
Test status
Simulation time 123702596 ps
CPU time 1.81 seconds
Started Aug 15 06:12:58 PM PDT 24
Finished Aug 15 06:13:00 PM PDT 24
Peak memory 215028 kb
Host smart-a0cc24c7-40cd-4793-80cd-811fd8209c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108078439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.108078439 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1294582340
Short name T788
Test name
Test status
Simulation time 665775801 ps
CPU time 3 seconds
Started Aug 15 06:12:56 PM PDT 24
Finished Aug 15 06:13:00 PM PDT 24
Peak memory 214980 kb
Host smart-23d468f7-dd5e-43df-8279-263760fa8b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294582340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1294
582340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2147372121
Short name T872
Test name
Test status
Simulation time 151173483 ps
CPU time 1.49 seconds
Started Aug 15 06:12:52 PM PDT 24
Finished Aug 15 06:12:54 PM PDT 24
Peak memory 221900 kb
Host smart-579025e6-2b31-4cb0-846b-d5529eb216b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147372121 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2147372121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2118265991
Short name T869
Test name
Test status
Simulation time 17637751 ps
CPU time 1.03 seconds
Started Aug 15 06:12:53 PM PDT 24
Finished Aug 15 06:12:54 PM PDT 24
Peak memory 206644 kb
Host smart-22d8cebf-6eb1-40d9-9130-a83abfff55f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118265991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2118265991 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.529821080
Short name T783
Test name
Test status
Simulation time 98387675 ps
CPU time 0.72 seconds
Started Aug 15 06:12:50 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 206388 kb
Host smart-e476dbca-a3cd-4e85-b88b-272f7fab646b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529821080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.529821080 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2140254283
Short name T728
Test name
Test status
Simulation time 96293262 ps
CPU time 1.53 seconds
Started Aug 15 06:12:50 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 215548 kb
Host smart-8fe99ce2-ca5a-4c1d-8f21-8283ac4349e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140254283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.2140254283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3365862417
Short name T95
Test name
Test status
Simulation time 114514269 ps
CPU time 1.37 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 215392 kb
Host smart-1d5c13fa-3889-4fdd-9ea4-dc7107b5b06e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365862417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3365862417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1844092859
Short name T850
Test name
Test status
Simulation time 120428022 ps
CPU time 2.42 seconds
Started Aug 15 06:13:10 PM PDT 24
Finished Aug 15 06:13:13 PM PDT 24
Peak memory 216008 kb
Host smart-a9d0d4f7-adf2-494c-b42e-6f3afcb96e0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844092859 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1844092859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1533468293
Short name T176
Test name
Test status
Simulation time 109721628 ps
CPU time 1.15 seconds
Started Aug 15 06:13:14 PM PDT 24
Finished Aug 15 06:13:15 PM PDT 24
Peak memory 214760 kb
Host smart-158e4360-6f87-4389-ae5c-11e3eee895b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533468293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1533468293 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3532450836
Short name T771
Test name
Test status
Simulation time 57677155 ps
CPU time 1.61 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:01 PM PDT 24
Peak memory 215352 kb
Host smart-28ae5da3-821b-465d-b1fb-9e71542f9587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532450836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.3532450836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2432666433
Short name T853
Test name
Test status
Simulation time 63107512 ps
CPU time 1.31 seconds
Started Aug 15 06:12:52 PM PDT 24
Finished Aug 15 06:12:53 PM PDT 24
Peak memory 215368 kb
Host smart-f47f14dc-a418-4556-a1a4-5eb1db5b36ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432666433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.2432666433 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.480357955
Short name T98
Test name
Test status
Simulation time 505197851 ps
CPU time 2.73 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215456 kb
Host smart-b8f6e533-d3f1-45cb-b13f-2b8eaf67f6e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480357955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.480357955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.179487340
Short name T114
Test name
Test status
Simulation time 192101212 ps
CPU time 3.12 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215048 kb
Host smart-cd422ff2-c027-41f3-a883-5fa58151cb56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179487340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.179487340 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3694070630
Short name T780
Test name
Test status
Simulation time 208195013 ps
CPU time 2.35 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 215136 kb
Host smart-510c8f5e-caff-4581-9148-01ef702233cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694070630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3694
070630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1161478574
Short name T796
Test name
Test status
Simulation time 155310988 ps
CPU time 2.35 seconds
Started Aug 15 06:13:14 PM PDT 24
Finished Aug 15 06:13:17 PM PDT 24
Peak memory 223064 kb
Host smart-abb89c65-520c-4491-8178-6cc813e0f3a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161478574 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1161478574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3644173818
Short name T751
Test name
Test status
Simulation time 19302471 ps
CPU time 0.99 seconds
Started Aug 15 06:12:57 PM PDT 24
Finished Aug 15 06:12:58 PM PDT 24
Peak memory 206480 kb
Host smart-3963883b-a2c4-42ed-aeca-7c9103b94fe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644173818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3644173818 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1964759096
Short name T119
Test name
Test status
Simulation time 102955992 ps
CPU time 0.72 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206412 kb
Host smart-3841809f-0dbd-4059-a28a-96c5a45f2f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964759096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1964759096 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1506779231
Short name T825
Test name
Test status
Simulation time 115947943 ps
CPU time 1.64 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 214932 kb
Host smart-a103f399-2ba7-4bae-a918-f5232d51ba51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506779231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1506779231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3983378416
Short name T806
Test name
Test status
Simulation time 117650643 ps
CPU time 1.23 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 215388 kb
Host smart-a99ece29-5bbc-4fbd-9ba4-c77f82665d69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983378416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3983378416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1733155995
Short name T803
Test name
Test status
Simulation time 48188632 ps
CPU time 1.73 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:06 PM PDT 24
Peak memory 215420 kb
Host smart-0d10a4a1-5f28-4cb0-b62f-8e83642b4f31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733155995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.1733155995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2481596940
Short name T134
Test name
Test status
Simulation time 233700706 ps
CPU time 2.67 seconds
Started Aug 15 06:13:15 PM PDT 24
Finished Aug 15 06:13:18 PM PDT 24
Peak memory 206776 kb
Host smart-5c1d7af7-78d0-4f0f-ab30-4bcca9f7b3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481596940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2481
596940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.679902734
Short name T832
Test name
Test status
Simulation time 493112787 ps
CPU time 2.39 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 216424 kb
Host smart-08f44216-7a5b-4107-a906-559b5e42bd2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679902734 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.679902734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.258575105
Short name T736
Test name
Test status
Simulation time 37525570 ps
CPU time 0.95 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:01 PM PDT 24
Peak memory 206476 kb
Host smart-ed0a43f4-549d-45b0-a5fe-c9d3b005de08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258575105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.258575105 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2466490999
Short name T828
Test name
Test status
Simulation time 56643985 ps
CPU time 0.79 seconds
Started Aug 15 06:12:56 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 206496 kb
Host smart-532c0ff5-6be4-4e2e-906d-2fa9b5245be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466490999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2466490999 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.697469769
Short name T151
Test name
Test status
Simulation time 118715356 ps
CPU time 2.56 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:06 PM PDT 24
Peak memory 215284 kb
Host smart-a794e16f-1375-4f58-b6f9-d6c7d7ba5b9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697469769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.697469769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3257054507
Short name T101
Test name
Test status
Simulation time 48350713 ps
CPU time 1.26 seconds
Started Aug 15 06:13:04 PM PDT 24
Finished Aug 15 06:13:06 PM PDT 24
Peak memory 215412 kb
Host smart-7f855636-e9cd-452a-b0ca-8e20ac91a494
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257054507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.3257054507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3539516569
Short name T815
Test name
Test status
Simulation time 137618644 ps
CPU time 2.93 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:05 PM PDT 24
Peak memory 215480 kb
Host smart-cc9ffc98-ce1e-4198-b4dd-f821ebb252f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539516569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.3539516569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2933040006
Short name T121
Test name
Test status
Simulation time 165732105 ps
CPU time 3.25 seconds
Started Aug 15 06:12:57 PM PDT 24
Finished Aug 15 06:13:00 PM PDT 24
Peak memory 214916 kb
Host smart-88c25834-86fa-4f29-b21d-3ca78550ed1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933040006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2933040006 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1985339378
Short name T801
Test name
Test status
Simulation time 198410777 ps
CPU time 2.77 seconds
Started Aug 15 06:13:31 PM PDT 24
Finished Aug 15 06:13:34 PM PDT 24
Peak memory 214956 kb
Host smart-e5602ceb-a921-4b8a-af0a-36e9e2437ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985339378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1985
339378 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1477661507
Short name T849
Test name
Test status
Simulation time 37900478 ps
CPU time 1.42 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:05 PM PDT 24
Peak memory 222108 kb
Host smart-777a33a4-cdce-4b64-a883-ddb76d3c6c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477661507 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1477661507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.2588302107
Short name T745
Test name
Test status
Simulation time 32605310 ps
CPU time 0.92 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206508 kb
Host smart-e465f946-5552-4689-bb1f-b8c0b4a2d260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588302107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2588302107 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.2080478877
Short name T778
Test name
Test status
Simulation time 16864291 ps
CPU time 0.79 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 206484 kb
Host smart-6148a7ac-5703-4df3-a1d3-159dc6c31a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080478877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2080478877 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.16708889
Short name T749
Test name
Test status
Simulation time 148659124 ps
CPU time 2.25 seconds
Started Aug 15 06:13:10 PM PDT 24
Finished Aug 15 06:13:13 PM PDT 24
Peak memory 215100 kb
Host smart-c4716fcc-efe1-4632-868c-ea1ddb8ca5d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16708889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_
outstanding.16708889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.220234292
Short name T800
Test name
Test status
Simulation time 165077358 ps
CPU time 0.96 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 215164 kb
Host smart-ae92e572-f818-44c8-afb7-b9edbe23ae41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220234292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_
errors.220234292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4098074244
Short name T96
Test name
Test status
Simulation time 91255852 ps
CPU time 2.27 seconds
Started Aug 15 06:12:59 PM PDT 24
Finished Aug 15 06:13:01 PM PDT 24
Peak memory 215492 kb
Host smart-5cc5a88b-ea12-41e6-a360-8d954f5ab305
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098074244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.4098074244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2960673597
Short name T841
Test name
Test status
Simulation time 443703469 ps
CPU time 3.22 seconds
Started Aug 15 06:13:12 PM PDT 24
Finished Aug 15 06:13:15 PM PDT 24
Peak memory 215060 kb
Host smart-f897f394-5797-455d-ae55-a17c9d238337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960673597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2960673597 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2790226758
Short name T829
Test name
Test status
Simulation time 159430849 ps
CPU time 4.07 seconds
Started Aug 15 06:13:08 PM PDT 24
Finished Aug 15 06:13:12 PM PDT 24
Peak memory 223372 kb
Host smart-125c013f-e859-4eac-a382-a15b70ec9b18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790226758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2790
226758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.20214725
Short name T135
Test name
Test status
Simulation time 71210650 ps
CPU time 2.4 seconds
Started Aug 15 06:13:16 PM PDT 24
Finished Aug 15 06:13:19 PM PDT 24
Peak memory 223188 kb
Host smart-c721b4cd-fee2-497b-9158-bd014b82e216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20214725 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.20214725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1766444626
Short name T760
Test name
Test status
Simulation time 28479302 ps
CPU time 0.9 seconds
Started Aug 15 06:13:15 PM PDT 24
Finished Aug 15 06:13:16 PM PDT 24
Peak memory 206480 kb
Host smart-516199d3-9530-433b-b8fe-ecc59dc60d8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766444626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1766444626 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2885484105
Short name T839
Test name
Test status
Simulation time 15482764 ps
CPU time 0.77 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206472 kb
Host smart-4af86172-7825-4358-a25e-03e49c3f77d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885484105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2885484105 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.4010554589
Short name T772
Test name
Test status
Simulation time 80103990 ps
CPU time 2.19 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 214992 kb
Host smart-cb16dfda-bc30-496f-9078-4919b6b5329c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010554589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.4010554589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1472156056
Short name T91
Test name
Test status
Simulation time 108500117 ps
CPU time 1.31 seconds
Started Aug 15 06:13:11 PM PDT 24
Finished Aug 15 06:13:12 PM PDT 24
Peak memory 215428 kb
Host smart-df6a9c74-61c1-4e3e-9586-15a8b159151a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472156056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1472156056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3281734281
Short name T802
Test name
Test status
Simulation time 117976910 ps
CPU time 3.13 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 215432 kb
Host smart-d14487f2-7383-4003-a40d-b081439a2e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281734281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3281734281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.19241241
Short name T115
Test name
Test status
Simulation time 926658885 ps
CPU time 3.26 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 215068 kb
Host smart-c28d3015-c1d8-4ef0-a59f-191b431f5622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19241241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.19241241 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.4288943130
Short name T112
Test name
Test status
Simulation time 74034554 ps
CPU time 2.47 seconds
Started Aug 15 06:13:04 PM PDT 24
Finished Aug 15 06:13:06 PM PDT 24
Peak memory 214988 kb
Host smart-29788086-feee-4766-a47e-2dec709a1870
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288943130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.4288
943130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2495138496
Short name T865
Test name
Test status
Simulation time 42283890 ps
CPU time 1.47 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:07 PM PDT 24
Peak memory 222900 kb
Host smart-bed76089-b623-4a4c-b5d8-c6c5d7a818d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495138496 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2495138496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.44894763
Short name T846
Test name
Test status
Simulation time 92056532 ps
CPU time 1.09 seconds
Started Aug 15 06:13:07 PM PDT 24
Finished Aug 15 06:13:08 PM PDT 24
Peak memory 206656 kb
Host smart-10fb365d-db9e-4af1-823f-ba65a38dc713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44894763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.44894763 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.606194376
Short name T758
Test name
Test status
Simulation time 12335686 ps
CPU time 0.76 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206452 kb
Host smart-e0fa42a2-ecdd-4642-83ea-bb8eaac81f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606194376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.606194376 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.578793993
Short name T146
Test name
Test status
Simulation time 397884852 ps
CPU time 2.39 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 215464 kb
Host smart-785636e6-543d-4b79-b267-3e681de9ed64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578793993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.578793993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2926588880
Short name T89
Test name
Test status
Simulation time 71097129 ps
CPU time 1.38 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 215396 kb
Host smart-679b6d7c-e3f1-4b22-8f9f-3ef2ddd723a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926588880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.2926588880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4254898167
Short name T868
Test name
Test status
Simulation time 171824857 ps
CPU time 2.3 seconds
Started Aug 15 06:13:10 PM PDT 24
Finished Aug 15 06:13:12 PM PDT 24
Peak memory 215424 kb
Host smart-a4f4dbda-e209-4564-9bfa-02f606a63a89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254898167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.4254898167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1385316028
Short name T116
Test name
Test status
Simulation time 246303840 ps
CPU time 2.02 seconds
Started Aug 15 06:13:21 PM PDT 24
Finished Aug 15 06:13:23 PM PDT 24
Peak memory 217600 kb
Host smart-e9f3f6d7-6b94-49a6-bd97-42389c32a53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385316028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1385316028 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3796337054
Short name T761
Test name
Test status
Simulation time 109489374 ps
CPU time 2.69 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206812 kb
Host smart-c1440dde-526d-461b-a474-10b27149fdf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796337054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3796
337054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.501325056
Short name T857
Test name
Test status
Simulation time 278384539 ps
CPU time 7.31 seconds
Started Aug 15 06:13:46 PM PDT 24
Finished Aug 15 06:13:53 PM PDT 24
Peak memory 214888 kb
Host smart-0da251b9-aa74-44f9-b74d-91b34615b9aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501325056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.50132505
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.556803846
Short name T862
Test name
Test status
Simulation time 6090252202 ps
CPU time 11.44 seconds
Started Aug 15 06:12:39 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 206720 kb
Host smart-7e51deef-0c7a-402b-bfaf-5ea30192ef82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556803846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.55680384
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1034240898
Short name T777
Test name
Test status
Simulation time 30427250 ps
CPU time 0.97 seconds
Started Aug 15 06:12:38 PM PDT 24
Finished Aug 15 06:12:39 PM PDT 24
Peak memory 206484 kb
Host smart-3312c0a5-4a34-418b-9722-390b39341b22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034240898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1034240
898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2874874065
Short name T133
Test name
Test status
Simulation time 197258487 ps
CPU time 1.72 seconds
Started Aug 15 06:12:45 PM PDT 24
Finished Aug 15 06:12:47 PM PDT 24
Peak memory 223112 kb
Host smart-d5fab05a-3943-49e3-895b-85858f95a0c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874874065 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2874874065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2189158968
Short name T848
Test name
Test status
Simulation time 61703455 ps
CPU time 0.89 seconds
Started Aug 15 06:14:06 PM PDT 24
Finished Aug 15 06:14:07 PM PDT 24
Peak memory 206496 kb
Host smart-512dcfc5-bb1c-459b-be37-5136563dbb76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189158968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2189158968 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.3403718096
Short name T769
Test name
Test status
Simulation time 44205122 ps
CPU time 0.76 seconds
Started Aug 15 06:12:41 PM PDT 24
Finished Aug 15 06:12:42 PM PDT 24
Peak memory 206472 kb
Host smart-57ad6fab-9e1d-4593-bff9-0dc784aaaef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403718096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3403718096 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2300848417
Short name T139
Test name
Test status
Simulation time 167652086 ps
CPU time 1.45 seconds
Started Aug 15 06:12:43 PM PDT 24
Finished Aug 15 06:12:45 PM PDT 24
Peak memory 214948 kb
Host smart-b3fbc9a1-d213-459b-baa0-aca60142ea70
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300848417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.2300848417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1332267414
Short name T738
Test name
Test status
Simulation time 18235498 ps
CPU time 0.71 seconds
Started Aug 15 06:12:32 PM PDT 24
Finished Aug 15 06:12:33 PM PDT 24
Peak memory 206432 kb
Host smart-2b077004-58d7-4599-9a93-5fa7a5b0e272
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332267414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1332267414
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3643091208
Short name T757
Test name
Test status
Simulation time 46009752 ps
CPU time 1.43 seconds
Started Aug 15 06:12:39 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 214960 kb
Host smart-04153875-3bb8-427d-a54e-918e8226f7dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643091208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.3643091208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3421622057
Short name T798
Test name
Test status
Simulation time 134839962 ps
CPU time 1.17 seconds
Started Aug 15 06:12:26 PM PDT 24
Finished Aug 15 06:12:27 PM PDT 24
Peak memory 215428 kb
Host smart-e7378e89-6489-4a6e-b80d-5227536735a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421622057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3421622057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3960859291
Short name T102
Test name
Test status
Simulation time 32758705 ps
CPU time 1.64 seconds
Started Aug 15 06:12:32 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 215492 kb
Host smart-9df6c853-5576-4629-af8b-2ef71d248b64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960859291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.3960859291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2098186499
Short name T125
Test name
Test status
Simulation time 90507938 ps
CPU time 2.4 seconds
Started Aug 15 06:13:49 PM PDT 24
Finished Aug 15 06:13:52 PM PDT 24
Peak memory 218428 kb
Host smart-a71e9d14-b60e-47a4-adc3-f90430ed4e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098186499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2098186499 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.3028149413
Short name T753
Test name
Test status
Simulation time 38319489 ps
CPU time 0.81 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206420 kb
Host smart-a2f8bb64-02bc-43c6-8741-26df45f43384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028149413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3028149413 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2802445231
Short name T746
Test name
Test status
Simulation time 18249486 ps
CPU time 0.8 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:01 PM PDT 24
Peak memory 206508 kb
Host smart-2919a979-333b-4658-b6f5-d2d57a8898d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802445231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2802445231 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.3652937749
Short name T750
Test name
Test status
Simulation time 27561203 ps
CPU time 0.84 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206420 kb
Host smart-45ce046b-e181-42b4-8fb9-f5dfe529a614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652937749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3652937749 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2533335094
Short name T755
Test name
Test status
Simulation time 22947424 ps
CPU time 0.77 seconds
Started Aug 15 06:13:13 PM PDT 24
Finished Aug 15 06:13:14 PM PDT 24
Peak memory 206456 kb
Host smart-246686de-cb43-4ed1-ab3f-8037ce5b4825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533335094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2533335094 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.1282779606
Short name T748
Test name
Test status
Simulation time 58921692 ps
CPU time 0.74 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:01 PM PDT 24
Peak memory 206492 kb
Host smart-278d06ac-ee7f-4d16-8e4e-d6ca66b39d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282779606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1282779606 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.1959438038
Short name T754
Test name
Test status
Simulation time 23395890 ps
CPU time 0.75 seconds
Started Aug 15 06:13:08 PM PDT 24
Finished Aug 15 06:13:09 PM PDT 24
Peak memory 206504 kb
Host smart-6d25aee6-5a53-40bf-9fbc-cc7063886367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959438038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1959438038 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.899537067
Short name T845
Test name
Test status
Simulation time 22065411 ps
CPU time 0.75 seconds
Started Aug 15 06:13:09 PM PDT 24
Finished Aug 15 06:13:10 PM PDT 24
Peak memory 206472 kb
Host smart-487e2888-7d12-497c-81b3-30b9ea941abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899537067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.899537067 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.943655177
Short name T742
Test name
Test status
Simulation time 58080870 ps
CPU time 0.73 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206460 kb
Host smart-88c2fed2-5d8b-4926-99cb-1f9de756f0a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943655177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.943655177 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.550042651
Short name T152
Test name
Test status
Simulation time 18298644 ps
CPU time 0.75 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206472 kb
Host smart-af707ab3-01ad-4518-9760-a4cfb8d28c67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550042651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.550042651 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.4275567909
Short name T831
Test name
Test status
Simulation time 37224254 ps
CPU time 0.75 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:13 PM PDT 24
Peak memory 206476 kb
Host smart-7e7b5b78-bf27-4009-83d5-8e779aac665a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275567909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4275567909 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.130078034
Short name T730
Test name
Test status
Simulation time 816689979 ps
CPU time 5.12 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:40 PM PDT 24
Peak memory 206568 kb
Host smart-7a4e24fa-c6e8-44c4-b7eb-82532418a120
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130078034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.13007803
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4033202999
Short name T752
Test name
Test status
Simulation time 649650953 ps
CPU time 8.07 seconds
Started Aug 15 06:12:39 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 206772 kb
Host smart-194480a0-a759-4d44-95f6-04abdde7b6a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033202999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.4033202
999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.159744241
Short name T733
Test name
Test status
Simulation time 27213504 ps
CPU time 1.06 seconds
Started Aug 15 06:12:32 PM PDT 24
Finished Aug 15 06:12:33 PM PDT 24
Peak memory 206664 kb
Host smart-239d1389-c77d-4732-a951-a5cb829f5a14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159744241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.15974424
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1446574467
Short name T817
Test name
Test status
Simulation time 297524783 ps
CPU time 2.35 seconds
Started Aug 15 06:12:38 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 223208 kb
Host smart-cb17e036-b6f8-4070-8d63-81f69dca9103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446574467 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1446574467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.335416270
Short name T153
Test name
Test status
Simulation time 37511828 ps
CPU time 0.91 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 206492 kb
Host smart-a0af9cd4-ffe4-40bd-b355-7441d77244f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335416270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.335416270 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1211823786
Short name T833
Test name
Test status
Simulation time 45647243 ps
CPU time 0.73 seconds
Started Aug 15 06:12:35 PM PDT 24
Finished Aug 15 06:12:36 PM PDT 24
Peak memory 206484 kb
Host smart-944dbbc8-a752-4dae-b0d2-c06dd06aef51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211823786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1211823786 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3818670879
Short name T140
Test name
Test status
Simulation time 41071182 ps
CPU time 1.51 seconds
Started Aug 15 06:12:41 PM PDT 24
Finished Aug 15 06:12:42 PM PDT 24
Peak memory 214860 kb
Host smart-223b6925-731c-4cd5-89ef-c900162baebc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818670879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.3818670879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2882399531
Short name T774
Test name
Test status
Simulation time 13432464 ps
CPU time 0.75 seconds
Started Aug 15 06:12:42 PM PDT 24
Finished Aug 15 06:12:43 PM PDT 24
Peak memory 206432 kb
Host smart-1b637723-6e9e-4094-85d8-cd208d92e4f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882399531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2882399531
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.592882974
Short name T794
Test name
Test status
Simulation time 387560871 ps
CPU time 2.43 seconds
Started Aug 15 06:12:40 PM PDT 24
Finished Aug 15 06:12:42 PM PDT 24
Peak memory 215040 kb
Host smart-41f50745-fb84-412f-acb6-53b9da242ff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592882974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_
outstanding.592882974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.602338155
Short name T797
Test name
Test status
Simulation time 88075114 ps
CPU time 0.99 seconds
Started Aug 15 06:12:51 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 215408 kb
Host smart-8b78409d-7664-4aaf-b5d9-0e451b98adcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602338155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.602338155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3807081560
Short name T840
Test name
Test status
Simulation time 49309777 ps
CPU time 1.48 seconds
Started Aug 15 06:12:40 PM PDT 24
Finished Aug 15 06:12:42 PM PDT 24
Peak memory 215444 kb
Host smart-f82bc9d0-e6b8-4c2d-b86f-9197a3e82525
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807081560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3807081560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.56140344
Short name T855
Test name
Test status
Simulation time 154763071 ps
CPU time 2.65 seconds
Started Aug 15 06:12:41 PM PDT 24
Finished Aug 15 06:12:44 PM PDT 24
Peak memory 215088 kb
Host smart-e6f4a1a1-ee23-4849-b9a9-7a4f5238fb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56140344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.56140344 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3700926186
Short name T765
Test name
Test status
Simulation time 86924897 ps
CPU time 2.56 seconds
Started Aug 15 06:12:32 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 217692 kb
Host smart-b1391e60-bc25-4cb2-9094-74f3c275efed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700926186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.37009
26186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.3571961047
Short name T847
Test name
Test status
Simulation time 30484304 ps
CPU time 0.77 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206404 kb
Host smart-6ff17c2a-d804-40b1-9b5e-a62f034edcb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571961047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3571961047 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.386886233
Short name T789
Test name
Test status
Simulation time 56054488 ps
CPU time 0.76 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:05 PM PDT 24
Peak memory 206480 kb
Host smart-34a0b2a5-71f1-45c6-8dd6-c4e9f1be7aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386886233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.386886233 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.61376376
Short name T835
Test name
Test status
Simulation time 158802358 ps
CPU time 0.76 seconds
Started Aug 15 06:13:11 PM PDT 24
Finished Aug 15 06:13:11 PM PDT 24
Peak memory 206508 kb
Host smart-48c76bb9-8086-4742-bbc9-52b6a1283485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61376376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.61376376 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.2146468587
Short name T168
Test name
Test status
Simulation time 14171788 ps
CPU time 0.76 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206404 kb
Host smart-c7ed07d7-ed8b-4cf8-9050-54c5de8a6eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146468587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2146468587 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.3614179139
Short name T807
Test name
Test status
Simulation time 22756454 ps
CPU time 0.76 seconds
Started Aug 15 06:13:07 PM PDT 24
Finished Aug 15 06:13:08 PM PDT 24
Peak memory 206512 kb
Host smart-12c8a400-43e3-460d-a346-0d8b4b44057c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614179139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3614179139 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.1892709912
Short name T820
Test name
Test status
Simulation time 11493728 ps
CPU time 0.77 seconds
Started Aug 15 06:13:06 PM PDT 24
Finished Aug 15 06:13:07 PM PDT 24
Peak memory 206512 kb
Host smart-62a9845f-e423-4d94-a127-038d031c7543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892709912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1892709912 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.1300928304
Short name T819
Test name
Test status
Simulation time 45535460 ps
CPU time 0.75 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206424 kb
Host smart-dd8211e7-bce0-4b0a-b7ed-4edeafb9d0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300928304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1300928304 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.3850928808
Short name T767
Test name
Test status
Simulation time 15813294 ps
CPU time 0.8 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 206472 kb
Host smart-9465c231-fc77-4e6c-ba8d-c8576c099d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850928808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3850928808 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1926382922
Short name T818
Test name
Test status
Simulation time 49668633 ps
CPU time 0.78 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206492 kb
Host smart-e878ff22-e9d5-48a2-b64a-b38a6d08eacf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926382922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1926382922 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.2461397222
Short name T166
Test name
Test status
Simulation time 26742005 ps
CPU time 0.77 seconds
Started Aug 15 06:13:03 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 206488 kb
Host smart-1394bd2b-6f7c-4e4e-831b-a28cc7dd0e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461397222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2461397222 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.635118603
Short name T148
Test name
Test status
Simulation time 376152166 ps
CPU time 5.23 seconds
Started Aug 15 06:12:38 PM PDT 24
Finished Aug 15 06:12:44 PM PDT 24
Peak memory 206760 kb
Host smart-6a1f29a9-f8c8-469c-a543-72b5b22653b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635118603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.63511860
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.4176471173
Short name T92
Test name
Test status
Simulation time 5781053431 ps
CPU time 21.08 seconds
Started Aug 15 06:12:51 PM PDT 24
Finished Aug 15 06:13:12 PM PDT 24
Peak memory 206772 kb
Host smart-b044f543-7832-434f-95e5-f22c58e3d49b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176471173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.4176471
173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1977969532
Short name T735
Test name
Test status
Simulation time 195670231 ps
CPU time 0.95 seconds
Started Aug 15 06:13:49 PM PDT 24
Finished Aug 15 06:13:55 PM PDT 24
Peak memory 206500 kb
Host smart-68e8d8f0-ca74-4242-bf38-15d51d9680bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977969532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1977969
532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3495143119
Short name T822
Test name
Test status
Simulation time 54842163 ps
CPU time 2.05 seconds
Started Aug 15 06:12:46 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 216588 kb
Host smart-7eac60db-8220-4340-9b2c-a3696075badd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495143119 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3495143119 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1145030129
Short name T93
Test name
Test status
Simulation time 17310483 ps
CPU time 0.89 seconds
Started Aug 15 06:12:46 PM PDT 24
Finished Aug 15 06:12:47 PM PDT 24
Peak memory 206368 kb
Host smart-b4ab3308-53db-4275-a7f3-786e598c4d36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145030129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1145030129 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.847081965
Short name T138
Test name
Test status
Simulation time 29129447 ps
CPU time 1.19 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:49 PM PDT 24
Peak memory 214860 kb
Host smart-b74b773c-7fdb-4b0e-b07b-25f78d128c18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847081965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial
_access.847081965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2954041348
Short name T768
Test name
Test status
Simulation time 20280972 ps
CPU time 0.71 seconds
Started Aug 15 06:12:42 PM PDT 24
Finished Aug 15 06:12:43 PM PDT 24
Peak memory 206508 kb
Host smart-043a9eb9-1181-4609-b0b7-f737f1f96817
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954041348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2954041348
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3311164421
Short name T811
Test name
Test status
Simulation time 104124743 ps
CPU time 2.47 seconds
Started Aug 15 06:12:54 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 215716 kb
Host smart-36f5b9a3-981c-454c-bbea-b535bac2227d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311164421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3311164421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.754279583
Short name T731
Test name
Test status
Simulation time 36066127 ps
CPU time 1.04 seconds
Started Aug 15 06:12:39 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 215460 kb
Host smart-66119eff-7b37-4e2c-bcb8-2dc839c380d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754279583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e
rrors.754279583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3151683934
Short name T149
Test name
Test status
Simulation time 243175773 ps
CPU time 2.74 seconds
Started Aug 15 06:12:34 PM PDT 24
Finished Aug 15 06:12:37 PM PDT 24
Peak memory 215488 kb
Host smart-5154b9e4-6659-435d-a1a5-29433680d752
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151683934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.3151683934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2420236672
Short name T49
Test name
Test status
Simulation time 103066072 ps
CPU time 2.65 seconds
Started Aug 15 06:13:49 PM PDT 24
Finished Aug 15 06:13:52 PM PDT 24
Peak memory 215012 kb
Host smart-425ac701-54dd-4fed-8d16-0845eacca4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420236672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2420236672 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.601084352
Short name T175
Test name
Test status
Simulation time 237811898 ps
CPU time 2.59 seconds
Started Aug 15 06:12:37 PM PDT 24
Finished Aug 15 06:12:40 PM PDT 24
Peak memory 214972 kb
Host smart-d24d8f61-601d-4efd-88ec-7aef3a486e34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601084352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.601084
352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.258892747
Short name T756
Test name
Test status
Simulation time 44942989 ps
CPU time 0.82 seconds
Started Aug 15 06:13:23 PM PDT 24
Finished Aug 15 06:13:24 PM PDT 24
Peak memory 206496 kb
Host smart-05a6dd24-4528-4ac9-bf87-029d02bda644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258892747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.258892747 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.244774147
Short name T162
Test name
Test status
Simulation time 33953554 ps
CPU time 0.76 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 206428 kb
Host smart-0564a563-d36f-495c-a77c-5b2643a44c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244774147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.244774147 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.3058889850
Short name T843
Test name
Test status
Simulation time 41293000 ps
CPU time 0.75 seconds
Started Aug 15 06:12:59 PM PDT 24
Finished Aug 15 06:13:05 PM PDT 24
Peak memory 206444 kb
Host smart-1486e25f-2ce4-4a6b-9880-1b244f3b00e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058889850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3058889850 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.4137047734
Short name T867
Test name
Test status
Simulation time 42615289 ps
CPU time 0.78 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206424 kb
Host smart-771a5c7f-6c60-438f-80b1-00855cc71f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137047734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4137047734 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1216644758
Short name T787
Test name
Test status
Simulation time 12682213 ps
CPU time 0.79 seconds
Started Aug 15 06:13:02 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 206480 kb
Host smart-8f6d8849-f208-4d2e-91a4-01217a466b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216644758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1216644758 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.1606973194
Short name T167
Test name
Test status
Simulation time 47671109 ps
CPU time 0.78 seconds
Started Aug 15 06:13:17 PM PDT 24
Finished Aug 15 06:13:18 PM PDT 24
Peak memory 206516 kb
Host smart-c5c7fefa-54ad-4608-81d4-125a6d98d551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606973194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1606973194 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1902890757
Short name T740
Test name
Test status
Simulation time 23572508 ps
CPU time 0.74 seconds
Started Aug 15 06:13:31 PM PDT 24
Finished Aug 15 06:13:31 PM PDT 24
Peak memory 206424 kb
Host smart-78c03eac-2d1e-495f-b350-6e9a49a0a400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902890757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1902890757 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1074207794
Short name T784
Test name
Test status
Simulation time 16064759 ps
CPU time 0.77 seconds
Started Aug 15 06:13:07 PM PDT 24
Finished Aug 15 06:13:08 PM PDT 24
Peak memory 206512 kb
Host smart-dcadd9b0-f59a-4ed5-80bf-ac40740ec909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074207794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1074207794 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.3481951397
Short name T118
Test name
Test status
Simulation time 53685116 ps
CPU time 0.83 seconds
Started Aug 15 06:13:14 PM PDT 24
Finished Aug 15 06:13:15 PM PDT 24
Peak memory 206464 kb
Host smart-b85c3fc9-93f3-4b0e-b954-95a2c0c99595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481951397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3481951397 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.223553283
Short name T743
Test name
Test status
Simulation time 49438110 ps
CPU time 0.74 seconds
Started Aug 15 06:13:00 PM PDT 24
Finished Aug 15 06:13:01 PM PDT 24
Peak memory 206472 kb
Host smart-474e1610-2efb-4282-8314-425225931db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223553283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.223553283 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3721680586
Short name T805
Test name
Test status
Simulation time 168112724 ps
CPU time 1.65 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:49 PM PDT 24
Peak memory 215040 kb
Host smart-21ed7548-ad4e-4023-83bd-0b523a44ea81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721680586 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3721680586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3587952908
Short name T150
Test name
Test status
Simulation time 53481193 ps
CPU time 1.14 seconds
Started Aug 15 06:12:57 PM PDT 24
Finished Aug 15 06:12:58 PM PDT 24
Peak memory 214932 kb
Host smart-ec5800b9-51b4-447e-aa1f-f78d852c78d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587952908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3587952908 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3707187168
Short name T809
Test name
Test status
Simulation time 15607259 ps
CPU time 0.74 seconds
Started Aug 15 06:12:40 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 206412 kb
Host smart-78e16c18-6c34-4695-81f2-9ac26906fb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707187168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3707187168 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.942653108
Short name T739
Test name
Test status
Simulation time 36606209 ps
CPU time 2.03 seconds
Started Aug 15 06:12:36 PM PDT 24
Finished Aug 15 06:12:39 PM PDT 24
Peak memory 215460 kb
Host smart-349d07ce-a49d-4f59-be44-3d2ccb0f3e40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942653108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.942653108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3039707237
Short name T863
Test name
Test status
Simulation time 75282372 ps
CPU time 1.24 seconds
Started Aug 15 06:12:53 PM PDT 24
Finished Aug 15 06:12:54 PM PDT 24
Peak memory 215496 kb
Host smart-bbecb79f-211b-4d54-8c7d-00f24a43bf5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039707237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.3039707237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.672041684
Short name T741
Test name
Test status
Simulation time 111163894 ps
CPU time 2.76 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215396 kb
Host smart-7f20d697-1705-421e-8a02-364e8fb38f67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672041684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.672041684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2240777171
Short name T126
Test name
Test status
Simulation time 234546033 ps
CPU time 3 seconds
Started Aug 15 06:12:56 PM PDT 24
Finished Aug 15 06:12:59 PM PDT 24
Peak memory 215000 kb
Host smart-ce8009ad-d202-4bad-8bf3-90b592da30f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240777171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2240777171 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1762775984
Short name T814
Test name
Test status
Simulation time 147834723 ps
CPU time 4.03 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 206816 kb
Host smart-4a1316bb-eeb2-4423-9733-ed48484691bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762775984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.17627
75984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2024543712
Short name T851
Test name
Test status
Simulation time 46154635 ps
CPU time 1.64 seconds
Started Aug 15 06:12:54 PM PDT 24
Finished Aug 15 06:12:56 PM PDT 24
Peak memory 214964 kb
Host smart-c043fd5a-a51e-46c0-8b35-9855ee31c3ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024543712 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2024543712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3499490162
Short name T785
Test name
Test status
Simulation time 71843769 ps
CPU time 0.95 seconds
Started Aug 15 06:12:43 PM PDT 24
Finished Aug 15 06:12:44 PM PDT 24
Peak memory 206404 kb
Host smart-819558b1-55c2-4f4e-8caa-8b67f0939116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499490162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3499490162 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.1907852966
Short name T870
Test name
Test status
Simulation time 18085531 ps
CPU time 0.78 seconds
Started Aug 15 06:12:44 PM PDT 24
Finished Aug 15 06:12:45 PM PDT 24
Peak memory 206416 kb
Host smart-269a0c55-e5f6-43eb-9db1-24515fb5a1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907852966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1907852966 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1353488738
Short name T790
Test name
Test status
Simulation time 367181506 ps
CPU time 2.9 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:50 PM PDT 24
Peak memory 215320 kb
Host smart-766576a0-7be2-4f25-b493-e711945416c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353488738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.1353488738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3998884738
Short name T781
Test name
Test status
Simulation time 46681978 ps
CPU time 0.83 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 206680 kb
Host smart-bcb0f386-511d-4cb9-9537-b2d2289b479b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998884738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3998884738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1379701997
Short name T90
Test name
Test status
Simulation time 364930218 ps
CPU time 1.6 seconds
Started Aug 15 06:12:50 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215052 kb
Host smart-cbe2d24e-571a-4859-840b-adfe100703f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379701997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1379701997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1195323777
Short name T169
Test name
Test status
Simulation time 360204360 ps
CPU time 2.31 seconds
Started Aug 15 06:12:50 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 215016 kb
Host smart-c1aa9df6-043d-4207-aedc-e54841da7628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195323777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1195323777 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1432749236
Short name T48
Test name
Test status
Simulation time 358363087 ps
CPU time 4.03 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 214904 kb
Host smart-0ac2564d-3514-4095-a535-57c3d2a03938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432749236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.14327
49236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1162519086
Short name T110
Test name
Test status
Simulation time 92327400 ps
CPU time 1.68 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 215552 kb
Host smart-6c53a604-25b3-4692-9ae4-17d1f2223a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162519086 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1162519086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1759551231
Short name T94
Test name
Test status
Simulation time 102233302 ps
CPU time 1.2 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:49 PM PDT 24
Peak memory 206756 kb
Host smart-56872b8f-15ca-4ae8-a5f5-65f913fb986b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759551231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1759551231 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1178004117
Short name T737
Test name
Test status
Simulation time 36531152 ps
CPU time 0.75 seconds
Started Aug 15 06:12:51 PM PDT 24
Finished Aug 15 06:12:52 PM PDT 24
Peak memory 206480 kb
Host smart-eb1b30f1-25e5-487f-8821-f97710826353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178004117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1178004117 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2361815873
Short name T795
Test name
Test status
Simulation time 101125690 ps
CPU time 2.28 seconds
Started Aug 15 06:12:42 PM PDT 24
Finished Aug 15 06:12:45 PM PDT 24
Peak memory 215236 kb
Host smart-975b4646-389f-471e-80bb-9bdfc0fe2ec3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361815873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2361815873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2308135580
Short name T864
Test name
Test status
Simulation time 22454013 ps
CPU time 1 seconds
Started Aug 15 06:12:39 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 215184 kb
Host smart-a1f1cd6d-81ed-4c51-b8f0-f96c16e9de1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308135580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2308135580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2218876299
Short name T99
Test name
Test status
Simulation time 56923408 ps
CPU time 2.55 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:50 PM PDT 24
Peak memory 215480 kb
Host smart-6b0ebcc0-9669-41f3-ac77-a34ddcdca896
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218876299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2218876299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2902213975
Short name T120
Test name
Test status
Simulation time 132738879 ps
CPU time 3.08 seconds
Started Aug 15 06:12:37 PM PDT 24
Finished Aug 15 06:12:40 PM PDT 24
Peak memory 214940 kb
Host smart-ee0630d3-e06d-4061-aa45-1579f0668e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902213975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2902213975 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.571135127
Short name T111
Test name
Test status
Simulation time 575106433 ps
CPU time 2.27 seconds
Started Aug 15 06:12:51 PM PDT 24
Finished Aug 15 06:12:53 PM PDT 24
Peak memory 216256 kb
Host smart-2f745a9f-4cfe-43fd-8048-039563090545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571135127 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.571135127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3164208259
Short name T812
Test name
Test status
Simulation time 77401770 ps
CPU time 0.9 seconds
Started Aug 15 06:12:53 PM PDT 24
Finished Aug 15 06:12:54 PM PDT 24
Peak memory 206444 kb
Host smart-15963b09-ed57-4166-afd6-6ad26a510fd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164208259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3164208259 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3623116038
Short name T165
Test name
Test status
Simulation time 21190982 ps
CPU time 0.76 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 206368 kb
Host smart-63e4b373-1c54-4929-a54d-40ff53c2d52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623116038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3623116038 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.232276313
Short name T766
Test name
Test status
Simulation time 440696931 ps
CPU time 2.55 seconds
Started Aug 15 06:12:48 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 215224 kb
Host smart-95e144c1-5723-4778-bd75-09a6de45f04d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232276313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_
outstanding.232276313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4246648303
Short name T808
Test name
Test status
Simulation time 152076864 ps
CPU time 2.98 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:50 PM PDT 24
Peak memory 214364 kb
Host smart-47004edf-60e1-45aa-b2d3-e33f7735fdd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246648303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.4246648303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2170181210
Short name T129
Test name
Test status
Simulation time 92288435 ps
CPU time 2.72 seconds
Started Aug 15 06:12:44 PM PDT 24
Finished Aug 15 06:12:47 PM PDT 24
Peak memory 215016 kb
Host smart-7106276a-1e66-4e04-ac38-78177d10745c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170181210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2170181210 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.679105582
Short name T132
Test name
Test status
Simulation time 188123052 ps
CPU time 2.53 seconds
Started Aug 15 06:12:46 PM PDT 24
Finished Aug 15 06:12:49 PM PDT 24
Peak memory 215284 kb
Host smart-2169f981-30c8-429a-abe9-019318810596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679105582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.679105
582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1568411992
Short name T130
Test name
Test status
Simulation time 39837244 ps
CPU time 2.39 seconds
Started Aug 15 06:12:50 PM PDT 24
Finished Aug 15 06:12:53 PM PDT 24
Peak memory 216544 kb
Host smart-e1e22f59-3ff8-47f0-8ff2-672f33302545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568411992 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1568411992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.4167758524
Short name T852
Test name
Test status
Simulation time 39636875 ps
CPU time 1.15 seconds
Started Aug 15 06:12:47 PM PDT 24
Finished Aug 15 06:12:48 PM PDT 24
Peak memory 214952 kb
Host smart-0f29100e-d72e-4ab0-9ddd-30e0b3aa837d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167758524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.4167758524 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.1609433923
Short name T813
Test name
Test status
Simulation time 47124703 ps
CPU time 0.76 seconds
Started Aug 15 06:13:01 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 206496 kb
Host smart-6d9e653a-bc13-4a3d-9d60-128d6f6e1480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609433923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1609433923 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1375910636
Short name T770
Test name
Test status
Simulation time 136249722 ps
CPU time 2.21 seconds
Started Aug 15 06:12:49 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 214920 kb
Host smart-0593d4e8-5687-4e8c-8047-7ff35dd6e208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375910636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.1375910636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.733268327
Short name T776
Test name
Test status
Simulation time 32627008 ps
CPU time 1.06 seconds
Started Aug 15 06:12:49 PM PDT 24
Finished Aug 15 06:12:50 PM PDT 24
Peak memory 215372 kb
Host smart-eb73979b-c35e-40c2-8a62-d5228027c090
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733268327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.733268327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3096800676
Short name T763
Test name
Test status
Simulation time 253748695 ps
CPU time 1.94 seconds
Started Aug 15 06:12:52 PM PDT 24
Finished Aug 15 06:12:54 PM PDT 24
Peak memory 215408 kb
Host smart-98f85f8b-1d12-4178-8cc7-506f0f2fba4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096800676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.3096800676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3301516592
Short name T122
Test name
Test status
Simulation time 64832986 ps
CPU time 1.71 seconds
Started Aug 15 06:12:51 PM PDT 24
Finished Aug 15 06:12:53 PM PDT 24
Peak memory 215064 kb
Host smart-89af4c2a-9899-43e0-9866-3b062ea1042e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301516592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3301516592 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3437883109
Short name T842
Test name
Test status
Simulation time 120593207 ps
CPU time 3.88 seconds
Started Aug 15 06:12:53 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 215004 kb
Host smart-a4e16615-0f83-495a-9983-ed0e6be56bfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437883109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.34378
83109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.2647272642
Short name T716
Test name
Test status
Simulation time 143288785 ps
CPU time 0.86 seconds
Started Aug 15 05:55:20 PM PDT 24
Finished Aug 15 05:55:21 PM PDT 24
Peak memory 204928 kb
Host smart-89355b77-683d-437e-a1b0-39081502923e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647272642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2647272642 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.3239944550
Short name T186
Test name
Test status
Simulation time 13495218719 ps
CPU time 43.65 seconds
Started Aug 15 05:55:24 PM PDT 24
Finished Aug 15 05:56:08 PM PDT 24
Peak memory 254040 kb
Host smart-5088819f-6af9-4f5a-a127-c95bea8ac296
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239944550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3239944550 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.2010693834
Short name T573
Test name
Test status
Simulation time 14073728119 ps
CPU time 290.04 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 06:00:18 PM PDT 24
Peak memory 467484 kb
Host smart-7db4f74a-e852-461f-a984-defcb8423ec0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010693834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_par
tial_data.2010693834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2038657775
Short name T595
Test name
Test status
Simulation time 110900612471 ps
CPU time 600.13 seconds
Started Aug 15 05:55:21 PM PDT 24
Finished Aug 15 06:05:22 PM PDT 24
Peak memory 245108 kb
Host smart-7fb65bdc-ad9f-463c-99b3-3c79f25ee50b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038657775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2038657775
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.914883761
Short name T206
Test name
Test status
Simulation time 975464381 ps
CPU time 24.56 seconds
Started Aug 15 05:55:22 PM PDT 24
Finished Aug 15 05:55:46 PM PDT 24
Peak memory 223464 kb
Host smart-dfb7785a-b04a-4123-8f9a-0c56ceecf7b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=914883761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.914883761 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.4082325713
Short name T654
Test name
Test status
Simulation time 2043114806 ps
CPU time 11.31 seconds
Started Aug 15 05:55:27 PM PDT 24
Finished Aug 15 05:55:38 PM PDT 24
Peak memory 223492 kb
Host smart-e63bbaa5-e4c6-4ef3-b705-2fdc029e7a94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4082325713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.4082325713 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.2540887417
Short name T669
Test name
Test status
Simulation time 1848142384 ps
CPU time 14.88 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 05:55:44 PM PDT 24
Peak memory 218320 kb
Host smart-bfffaf2e-edbc-4852-bebe-94592c2dcbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540887417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2540887417 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.4009352769
Short name T320
Test name
Test status
Simulation time 535310734 ps
CPU time 15.6 seconds
Started Aug 15 05:55:35 PM PDT 24
Finished Aug 15 05:55:51 PM PDT 24
Peak memory 223780 kb
Host smart-a73c2f73-e7d6-4c09-9e37-d3947d5f3683
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009352769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.40
09352769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.1433301500
Short name T108
Test name
Test status
Simulation time 1344090858 ps
CPU time 101.3 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 05:57:11 PM PDT 24
Peak memory 272836 kb
Host smart-f374d538-de7d-4896-8ed7-48e5c993e182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433301500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1433301500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.483941982
Short name T487
Test name
Test status
Simulation time 16390807210 ps
CPU time 8.92 seconds
Started Aug 15 05:55:31 PM PDT 24
Finished Aug 15 05:55:40 PM PDT 24
Peak memory 217768 kb
Host smart-35cbc6da-b88f-4a81-9e2b-33b9312d3b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483941982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.483941982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.3162704298
Short name T411
Test name
Test status
Simulation time 38068131 ps
CPU time 1.26 seconds
Started Aug 15 05:55:20 PM PDT 24
Finished Aug 15 05:55:22 PM PDT 24
Peak memory 218388 kb
Host smart-a07fd05f-c8d6-40a8-823d-4e9ac591a3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162704298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3162704298 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.4210115451
Short name T723
Test name
Test status
Simulation time 5313643958 ps
CPU time 468.41 seconds
Started Aug 15 05:55:31 PM PDT 24
Finished Aug 15 06:03:20 PM PDT 24
Peak memory 545168 kb
Host smart-3dfd89a6-3195-42aa-a3e7-f3c0589a07b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210115451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.4210115451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.573536687
Short name T21
Test name
Test status
Simulation time 9042159439 ps
CPU time 251.26 seconds
Started Aug 15 05:55:25 PM PDT 24
Finished Aug 15 05:59:36 PM PDT 24
Peak memory 436240 kb
Host smart-a0c3846c-e47f-4b32-ba33-f19cd39bff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573536687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.573536687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2523562819
Short name T69
Test name
Test status
Simulation time 17943804829 ps
CPU time 57.53 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 05:56:26 PM PDT 24
Peak memory 259856 kb
Host smart-e2c13082-5d07-4dd4-8b7b-28b46bd31b1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523562819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2523562819 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.1311556863
Short name T659
Test name
Test status
Simulation time 909122609 ps
CPU time 12.27 seconds
Started Aug 15 05:55:23 PM PDT 24
Finished Aug 15 05:55:35 PM PDT 24
Peak memory 220896 kb
Host smart-8f980423-867c-4a38-af98-7ebff8868bba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311556863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1311556863 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.379437567
Short name T670
Test name
Test status
Simulation time 658019433 ps
CPU time 8.86 seconds
Started Aug 15 05:55:23 PM PDT 24
Finished Aug 15 05:55:32 PM PDT 24
Peak memory 217892 kb
Host smart-7ce9a5d0-3746-4d32-bae7-4d611abd13ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379437567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.379437567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.1520906945
Short name T81
Test name
Test status
Simulation time 2638550254 ps
CPU time 143.23 seconds
Started Aug 15 05:55:24 PM PDT 24
Finished Aug 15 05:57:48 PM PDT 24
Peak memory 273960 kb
Host smart-06e308d1-aa51-452d-9206-2a5a24bf6af5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1520906945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1520906945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.2089479817
Short name T290
Test name
Test status
Simulation time 130266875 ps
CPU time 2.49 seconds
Started Aug 15 05:55:26 PM PDT 24
Finished Aug 15 05:55:29 PM PDT 24
Peak memory 217676 kb
Host smart-bf32f95f-d690-4f1a-9c0b-9d21453af65d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089479817 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.2089479817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.692791998
Short name T286
Test name
Test status
Simulation time 98998695 ps
CPU time 2.49 seconds
Started Aug 15 05:55:26 PM PDT 24
Finished Aug 15 05:55:29 PM PDT 24
Peak memory 217568 kb
Host smart-fe8aed3d-53aa-4984-ab1f-9d9fc51aa9e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692791998 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.kmac_test_vectors_kmac_xof.692791998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.4118340480
Short name T73
Test name
Test status
Simulation time 18110819267 ps
CPU time 1704.17 seconds
Started Aug 15 05:55:31 PM PDT 24
Finished Aug 15 06:23:56 PM PDT 24
Peak memory 1179048 kb
Host smart-4576619f-2a4d-431f-9f6a-cabc4edc1afd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4118340480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.4118340480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.2840605556
Short name T618
Test name
Test status
Simulation time 70087606993 ps
CPU time 1658.52 seconds
Started Aug 15 05:55:26 PM PDT 24
Finished Aug 15 06:23:05 PM PDT 24
Peak memory 1126708 kb
Host smart-30ad02dc-089a-4320-b699-d160b19d24b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2840605556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2840605556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.1611718131
Short name T661
Test name
Test status
Simulation time 13070873380 ps
CPU time 1196.47 seconds
Started Aug 15 05:55:27 PM PDT 24
Finished Aug 15 06:15:23 PM PDT 24
Peak memory 921312 kb
Host smart-d0ee626e-336c-4649-af39-63f5a2160083
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1611718131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1611718131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.2186192823
Short name T15
Test name
Test status
Simulation time 95989092586 ps
CPU time 1511.12 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 06:20:39 PM PDT 24
Peak memory 1715640 kb
Host smart-1b7e9591-d642-40d1-81e8-5d7c69a1695f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2186192823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2186192823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.2773306177
Short name T479
Test name
Test status
Simulation time 57193060401 ps
CPU time 232.95 seconds
Started Aug 15 05:55:34 PM PDT 24
Finished Aug 15 05:59:27 PM PDT 24
Peak memory 270304 kb
Host smart-96c3f44c-a478-4664-b3ac-634bb9d8e16f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2773306177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2773306177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.1436459515
Short name T461
Test name
Test status
Simulation time 30904666229 ps
CPU time 367.43 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 06:01:36 PM PDT 24
Peak memory 350180 kb
Host smart-b13e215e-db73-4f5a-9fe4-2dc56e3b9b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1436459515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1436459515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.4275833250
Short name T560
Test name
Test status
Simulation time 26334491 ps
CPU time 0.8 seconds
Started Aug 15 05:55:30 PM PDT 24
Finished Aug 15 05:55:31 PM PDT 24
Peak memory 204964 kb
Host smart-dd755490-c3c2-442c-ad73-6510ae5a276d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275833250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.4275833250 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.1116943216
Short name T473
Test name
Test status
Simulation time 68969528471 ps
CPU time 255.45 seconds
Started Aug 15 05:55:31 PM PDT 24
Finished Aug 15 05:59:47 PM PDT 24
Peak memory 429664 kb
Host smart-4132268c-e0a7-4fb6-ac85-e9bd90acba22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116943216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1116943216 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.2014300145
Short name T428
Test name
Test status
Simulation time 14896474996 ps
CPU time 83.37 seconds
Started Aug 15 05:55:30 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 292080 kb
Host smart-e58ccbac-ed00-4481-bbd5-d98e1ef2d463
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014300145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.2014300145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.2097549226
Short name T536
Test name
Test status
Simulation time 28995815689 ps
CPU time 542.99 seconds
Started Aug 15 05:55:31 PM PDT 24
Finished Aug 15 06:04:34 PM PDT 24
Peak memory 244832 kb
Host smart-36fb12c4-e8bb-41e7-9917-68c0247ca335
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097549226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2097549226
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3531129375
Short name T561
Test name
Test status
Simulation time 2432233941 ps
CPU time 19.73 seconds
Started Aug 15 05:55:27 PM PDT 24
Finished Aug 15 05:55:47 PM PDT 24
Peak memory 223560 kb
Host smart-10626115-e170-4ef5-8510-2cdef9182f54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3531129375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3531129375 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2439384902
Short name T228
Test name
Test status
Simulation time 1680395240 ps
CPU time 31.72 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:56:05 PM PDT 24
Peak memory 223592 kb
Host smart-999e97a9-31bc-4726-8364-18111796c71f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2439384902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2439384902 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.2969141718
Short name T41
Test name
Test status
Simulation time 18745434977 ps
CPU time 54.38 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 218288 kb
Host smart-ef12ccc3-4328-4ef3-bbb9-ac9dd1996817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969141718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2969141718 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.3971865991
Short name T621
Test name
Test status
Simulation time 13774991954 ps
CPU time 306.27 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 06:00:39 PM PDT 24
Peak memory 475828 kb
Host smart-f89629d1-e654-438f-9dc1-96ca30e98212
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971865991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.39
71865991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.3271991981
Short name T266
Test name
Test status
Simulation time 4196074039 ps
CPU time 122.64 seconds
Started Aug 15 05:55:30 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 322660 kb
Host smart-58c02ac6-13f1-4ffa-a982-be647edd652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271991981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3271991981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.8428909
Short name T711
Test name
Test status
Simulation time 1474673253 ps
CPU time 7.7 seconds
Started Aug 15 05:55:34 PM PDT 24
Finished Aug 15 05:55:42 PM PDT 24
Peak memory 217384 kb
Host smart-42d4c4c6-1627-484d-b7b6-dc300c969023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8428909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.8428909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.559250300
Short name T214
Test name
Test status
Simulation time 119727042 ps
CPU time 1.34 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 05:55:30 PM PDT 24
Peak memory 216996 kb
Host smart-c7b5559f-7c3e-46af-8933-766313bacc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559250300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.559250300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1808665322
Short name T364
Test name
Test status
Simulation time 1446660019 ps
CPU time 63.22 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:56:35 PM PDT 24
Peak memory 251424 kb
Host smart-2d438869-8641-43eb-9c82-e867f4548634
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808665322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1808665322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.1016812103
Short name T685
Test name
Test status
Simulation time 7275509575 ps
CPU time 76.1 seconds
Started Aug 15 05:55:40 PM PDT 24
Finished Aug 15 05:56:56 PM PDT 24
Peak memory 289044 kb
Host smart-baf53329-0ea7-46d2-8af7-9bb8d78f7a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016812103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1016812103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.2212769436
Short name T70
Test name
Test status
Simulation time 9549124832 ps
CPU time 31.25 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:56:04 PM PDT 24
Peak memory 247416 kb
Host smart-7c713dc5-a871-4ee5-b029-598670197978
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212769436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2212769436 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.1247128691
Short name T643
Test name
Test status
Simulation time 16401518764 ps
CPU time 241.99 seconds
Started Aug 15 05:55:34 PM PDT 24
Finished Aug 15 05:59:36 PM PDT 24
Peak memory 447340 kb
Host smart-218e8f13-bcbe-4239-a7e7-e4880464dcfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247128691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1247128691 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2598179359
Short name T598
Test name
Test status
Simulation time 101401195 ps
CPU time 5.63 seconds
Started Aug 15 05:55:23 PM PDT 24
Finished Aug 15 05:55:29 PM PDT 24
Peak memory 217880 kb
Host smart-4bf437bc-84ba-4281-9339-61dff30c5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598179359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2598179359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.3106605634
Short name T79
Test name
Test status
Simulation time 6084853256 ps
CPU time 164.01 seconds
Started Aug 15 05:55:35 PM PDT 24
Finished Aug 15 05:58:19 PM PDT 24
Peak memory 296764 kb
Host smart-e6f941a9-2d2c-4466-9a12-91ba62a6c907
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3106605634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3106605634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.2716633559
Short name T520
Test name
Test status
Simulation time 119975068 ps
CPU time 2.13 seconds
Started Aug 15 05:55:38 PM PDT 24
Finished Aug 15 05:55:41 PM PDT 24
Peak memory 217756 kb
Host smart-c90f3e6e-59e4-4fa5-969d-be6bc0fd4d9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716633559 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.2716633559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.526034562
Short name T190
Test name
Test status
Simulation time 28240574 ps
CPU time 1.86 seconds
Started Aug 15 05:55:34 PM PDT 24
Finished Aug 15 05:55:36 PM PDT 24
Peak memory 217512 kb
Host smart-0a0c43c1-6f4f-40e7-9170-9b3cc30ce983
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526034562 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.kmac_test_vectors_kmac_xof.526034562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.1604232186
Short name T557
Test name
Test status
Simulation time 42447329984 ps
CPU time 1748.4 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 06:24:41 PM PDT 24
Peak memory 1155956 kb
Host smart-1e27f01b-06a1-4512-88b7-a245cdc68b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1604232186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1604232186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.105617903
Short name T360
Test name
Test status
Simulation time 14128327114 ps
CPU time 45.49 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:56:19 PM PDT 24
Peak memory 243908 kb
Host smart-d1744901-5ddf-4f60-bc38-e43706026d21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=105617903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.105617903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.175596370
Short name T325
Test name
Test status
Simulation time 282625528164 ps
CPU time 2152.22 seconds
Started Aug 15 05:55:25 PM PDT 24
Finished Aug 15 06:31:18 PM PDT 24
Peak memory 2378112 kb
Host smart-3cc58821-a504-4e42-8f87-629e152fc052
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=175596370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.175596370 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.86870680
Short name T615
Test name
Test status
Simulation time 44638694142 ps
CPU time 867.26 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 06:09:56 PM PDT 24
Peak memory 689924 kb
Host smart-394ba581-f34f-4fb3-8dac-d15b527025fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=86870680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.86870680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1836438206
Short name T539
Test name
Test status
Simulation time 20359669420 ps
CPU time 2118.36 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 06:30:48 PM PDT 24
Peak memory 1319776 kb
Host smart-fca6fb4c-f6ce-4ea1-921b-b2198ec60ac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1836438206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1836438206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3079089551
Short name T292
Test name
Test status
Simulation time 31888673626 ps
CPU time 335.47 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 253028 kb
Host smart-8c32fb3c-4262-4d55-8f30-18dedeb9d67b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3079089551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3079089551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_app.530521677
Short name T349
Test name
Test status
Simulation time 77377448958 ps
CPU time 381.21 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 06:02:31 PM PDT 24
Peak memory 554552 kb
Host smart-b9b208a1-feca-4403-aaf1-0df5e06a135b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530521677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.530521677 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.607493219
Short name T143
Test name
Test status
Simulation time 4515728840 ps
CPU time 165.12 seconds
Started Aug 15 05:56:02 PM PDT 24
Finished Aug 15 05:58:47 PM PDT 24
Peak memory 228064 kb
Host smart-408a984f-1d04-4419-b091-6dbc8b082e7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607493219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.607493219
+enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.4244046123
Short name T408
Test name
Test status
Simulation time 6360748440 ps
CPU time 17.34 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:26 PM PDT 24
Peak memory 217804 kb
Host smart-166af189-1201-450e-b1d1-a7b52e7509b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4244046123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.4244046123 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.3099448933
Short name T672
Test name
Test status
Simulation time 60343984 ps
CPU time 2.61 seconds
Started Aug 15 05:55:58 PM PDT 24
Finished Aug 15 05:56:00 PM PDT 24
Peak memory 216380 kb
Host smart-413edda3-a8ac-49bd-929d-4a25a6300eab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3099448933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3099448933 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.1069217002
Short name T309
Test name
Test status
Simulation time 1413509964 ps
CPU time 26.41 seconds
Started Aug 15 05:56:02 PM PDT 24
Finished Aug 15 05:56:28 PM PDT 24
Peak memory 252648 kb
Host smart-c2204b0a-f083-4adb-9a4f-f0283920afb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069217002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1
069217002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.217987057
Short name T478
Test name
Test status
Simulation time 20679388625 ps
CPU time 460.53 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 06:03:49 PM PDT 24
Peak memory 666140 kb
Host smart-6c1541bf-f5f1-4301-9874-58d002875ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217987057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.217987057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.4235784598
Short name T697
Test name
Test status
Simulation time 4302479569 ps
CPU time 8.29 seconds
Started Aug 15 05:55:53 PM PDT 24
Finished Aug 15 05:56:02 PM PDT 24
Peak memory 217784 kb
Host smart-1300987d-1b83-4d21-ba0a-8b9b17c14d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235784598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.4235784598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.252146279
Short name T55
Test name
Test status
Simulation time 138532751 ps
CPU time 1.41 seconds
Started Aug 15 05:56:00 PM PDT 24
Finished Aug 15 05:56:02 PM PDT 24
Peak memory 218476 kb
Host smart-b2530885-0ba3-4463-8739-8eff7343152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252146279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.252146279 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_sideload.72356563
Short name T639
Test name
Test status
Simulation time 2098307775 ps
CPU time 37.92 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 05:56:39 PM PDT 24
Peak memory 234616 kb
Host smart-4507f2e6-14e6-4eb8-8eaf-6c4ddec023ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72356563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.72356563 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.4274544927
Short name T423
Test name
Test status
Simulation time 793938450 ps
CPU time 41.48 seconds
Started Aug 15 05:56:17 PM PDT 24
Finished Aug 15 05:56:59 PM PDT 24
Peak memory 218084 kb
Host smart-0886b7bf-f75f-45b5-a571-71385bac9ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274544927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.4274544927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_alert_test.4256376519
Short name T531
Test name
Test status
Simulation time 16468323 ps
CPU time 0.76 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:56:20 PM PDT 24
Peak memory 204936 kb
Host smart-198c44b2-4ca4-4f0d-9b37-c311ef07a077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256376519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.4256376519 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2894901447
Short name T395
Test name
Test status
Simulation time 10032528187 ps
CPU time 125.78 seconds
Started Aug 15 05:56:13 PM PDT 24
Finished Aug 15 05:58:19 PM PDT 24
Peak memory 273480 kb
Host smart-8f279bef-a398-4ca8-88e8-ddad5f7a970f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894901447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2894901447 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.684928820
Short name T144
Test name
Test status
Simulation time 10528014289 ps
CPU time 78.16 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 05:57:27 PM PDT 24
Peak memory 222048 kb
Host smart-b70b6412-1b6f-4c0f-ba77-62823b2c5334
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684928820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.684928820
+enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1968250355
Short name T179
Test name
Test status
Simulation time 4529379298 ps
CPU time 40.35 seconds
Started Aug 15 05:56:17 PM PDT 24
Finished Aug 15 05:56:57 PM PDT 24
Peak memory 223524 kb
Host smart-eb36ff6f-15a1-4d5f-ad15-75622892262a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968250355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1968250355 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1144027268
Short name T65
Test name
Test status
Simulation time 488294339 ps
CPU time 10.98 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 05:56:27 PM PDT 24
Peak memory 215192 kb
Host smart-69ad758a-4f7d-4958-8846-c55f550db8aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1144027268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1144027268 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_error.1604630609
Short name T24
Test name
Test status
Simulation time 12844399655 ps
CPU time 366.38 seconds
Started Aug 15 05:55:51 PM PDT 24
Finished Aug 15 06:01:58 PM PDT 24
Peak memory 550948 kb
Host smart-1f8962fc-e975-4cbd-9b08-4eccb646d454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604630609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1604630609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.3746474645
Short name T378
Test name
Test status
Simulation time 92705458 ps
CPU time 1.29 seconds
Started Aug 15 05:56:12 PM PDT 24
Finished Aug 15 05:56:13 PM PDT 24
Peak memory 217716 kb
Host smart-374d6383-7840-4bcf-b0a9-2732f2475114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746474645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3746474645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.3135600041
Short name T691
Test name
Test status
Simulation time 81763323 ps
CPU time 1.35 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:16 PM PDT 24
Peak memory 217552 kb
Host smart-989111fc-5841-4018-afde-251a55b51e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135600041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3135600041 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1227859775
Short name T565
Test name
Test status
Simulation time 75160161507 ps
CPU time 2891.04 seconds
Started Aug 15 05:55:52 PM PDT 24
Finished Aug 15 06:44:03 PM PDT 24
Peak memory 1676516 kb
Host smart-0f6d04d5-02f1-4631-aea3-7ae8b91950cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227859775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1227859775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1277255083
Short name T623
Test name
Test status
Simulation time 3272652593 ps
CPU time 250.94 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 06:00:12 PM PDT 24
Peak memory 321880 kb
Host smart-03d18b20-8ca8-4f29-8fd8-987d0a5e869f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277255083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1277255083 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.2610156323
Short name T321
Test name
Test status
Simulation time 6046134619 ps
CPU time 27.28 seconds
Started Aug 15 05:55:57 PM PDT 24
Finished Aug 15 05:56:25 PM PDT 24
Peak memory 218380 kb
Host smart-4d688221-9253-4a4c-a768-1aa34488ae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610156323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2610156323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.3811464703
Short name T705
Test name
Test status
Simulation time 14650586902 ps
CPU time 380.26 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 06:02:43 PM PDT 24
Peak memory 505484 kb
Host smart-582502f3-2bad-4912-9251-3c85f8593236
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3811464703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3811464703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1827820752
Short name T434
Test name
Test status
Simulation time 77859319 ps
CPU time 0.82 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 05:56:00 PM PDT 24
Peak memory 204952 kb
Host smart-c2e6b207-2db5-4b67-b883-029e679f74f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827820752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1827820752 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.3304465039
Short name T724
Test name
Test status
Simulation time 7536955802 ps
CPU time 145.65 seconds
Started Aug 15 05:56:02 PM PDT 24
Finished Aug 15 05:58:28 PM PDT 24
Peak memory 339468 kb
Host smart-273899e7-5f10-408a-8c73-58ed620fb7ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304465039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3304465039 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.1173399616
Short name T236
Test name
Test status
Simulation time 10661246418 ps
CPU time 201.49 seconds
Started Aug 15 05:56:04 PM PDT 24
Finished Aug 15 05:59:26 PM PDT 24
Peak memory 228380 kb
Host smart-ef962cd1-01b5-4e2d-b310-95299c2c1e55
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173399616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.117339961
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3880120392
Short name T259
Test name
Test status
Simulation time 2687867255 ps
CPU time 18.03 seconds
Started Aug 15 05:55:58 PM PDT 24
Finished Aug 15 05:56:16 PM PDT 24
Peak memory 223680 kb
Host smart-d4a90c83-8394-42b3-8a41-d73d677ba5d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3880120392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3880120392 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.1668661503
Short name T567
Test name
Test status
Simulation time 979864178 ps
CPU time 11.72 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:56:33 PM PDT 24
Peak memory 223340 kb
Host smart-6b309705-85d1-4c04-a4d8-0e80e9e2ebbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1668661503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1668661503 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.2268622563
Short name T310
Test name
Test status
Simulation time 27854926477 ps
CPU time 165.26 seconds
Started Aug 15 05:56:03 PM PDT 24
Finished Aug 15 05:58:49 PM PDT 24
Peak memory 362288 kb
Host smart-427f849b-d1ba-4721-8be6-3ecc751bd293
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268622563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2
268622563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.166583863
Short name T302
Test name
Test status
Simulation time 3665361204 ps
CPU time 282.86 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 06:01:02 PM PDT 24
Peak memory 341056 kb
Host smart-3b957b4f-97a2-4d74-967b-ada7653a7326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166583863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.166583863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.68968670
Short name T343
Test name
Test status
Simulation time 1617874293 ps
CPU time 3 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:56:22 PM PDT 24
Peak memory 217396 kb
Host smart-42e2d77b-bcc3-46eb-a7b8-862e88961bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68968670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.68968670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.4001196625
Short name T32
Test name
Test status
Simulation time 39166351 ps
CPU time 1.26 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 218496 kb
Host smart-a7ef4879-bd44-48c6-a845-01ae282c3113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001196625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.4001196625 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.2870002080
Short name T611
Test name
Test status
Simulation time 98230188834 ps
CPU time 3794.63 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 06:59:25 PM PDT 24
Peak memory 3163828 kb
Host smart-b7ef9233-733e-4072-b73c-f4aa21b3e874
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870002080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.2870002080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1934813218
Short name T612
Test name
Test status
Simulation time 5425368391 ps
CPU time 89.68 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 05:57:29 PM PDT 24
Peak memory 259460 kb
Host smart-6c2597cf-8b76-4e3e-97b2-6b0db4df99a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934813218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1934813218 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.979253381
Short name T471
Test name
Test status
Simulation time 1125834605 ps
CPU time 18.59 seconds
Started Aug 15 05:56:02 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 217852 kb
Host smart-95a175d0-99aa-4284-b33c-2a8aafeec6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979253381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.979253381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.2170826559
Short name T634
Test name
Test status
Simulation time 88044852033 ps
CPU time 555.83 seconds
Started Aug 15 05:56:00 PM PDT 24
Finished Aug 15 06:05:16 PM PDT 24
Peak memory 461864 kb
Host smart-529ad6ca-a797-4a33-bafc-bd6ebcc03860
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2170826559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2170826559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_alert_test.762744246
Short name T715
Test name
Test status
Simulation time 21990799 ps
CPU time 0.78 seconds
Started Aug 15 05:56:04 PM PDT 24
Finished Aug 15 05:56:05 PM PDT 24
Peak memory 204944 kb
Host smart-4537e4a0-f930-447f-a680-4b276f3f1c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762744246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.762744246 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.3518225136
Short name T718
Test name
Test status
Simulation time 10864226214 ps
CPU time 158.88 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:58:45 PM PDT 24
Peak memory 355448 kb
Host smart-c455d2a8-9e3d-4689-92cc-0ce3a3114f39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518225136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3518225136 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.4073179115
Short name T720
Test name
Test status
Simulation time 90408084979 ps
CPU time 573.4 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 06:05:49 PM PDT 24
Peak memory 244588 kb
Host smart-184468e2-c200-471c-ba1c-bdff27907098
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073179115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.407317911
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.1896856026
Short name T335
Test name
Test status
Simulation time 1823247751 ps
CPU time 33.7 seconds
Started Aug 15 05:56:03 PM PDT 24
Finished Aug 15 05:56:36 PM PDT 24
Peak memory 220836 kb
Host smart-c3a7ef2a-353f-4b1d-bb7c-86b1f5b4802e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1896856026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.1896856026 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.503238005
Short name T417
Test name
Test status
Simulation time 1467427028 ps
CPU time 42.63 seconds
Started Aug 15 05:56:17 PM PDT 24
Finished Aug 15 05:57:00 PM PDT 24
Peak memory 223588 kb
Host smart-100cb10d-3551-4115-875f-ffbd74ec4054
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503238005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.503238005 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.856900785
Short name T663
Test name
Test status
Simulation time 5431223808 ps
CPU time 259.34 seconds
Started Aug 15 05:56:05 PM PDT 24
Finished Aug 15 06:00:24 PM PDT 24
Peak memory 321444 kb
Host smart-1614b26e-5aa8-4889-b2a1-62cc177fecb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856900785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.85
6900785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2702669687
Short name T726
Test name
Test status
Simulation time 9216478170 ps
CPU time 226.81 seconds
Started Aug 15 05:56:02 PM PDT 24
Finished Aug 15 05:59:49 PM PDT 24
Peak memory 322024 kb
Host smart-3b0f15ff-486a-4005-a3ad-9fd24a82a329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702669687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2702669687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.3065635606
Short name T551
Test name
Test status
Simulation time 6410818249 ps
CPU time 8.53 seconds
Started Aug 15 05:55:58 PM PDT 24
Finished Aug 15 05:56:07 PM PDT 24
Peak memory 217744 kb
Host smart-11a71148-8602-4b55-8fae-2587fd69f7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065635606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3065635606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.3754581527
Short name T398
Test name
Test status
Simulation time 443043182 ps
CPU time 3.79 seconds
Started Aug 15 05:56:04 PM PDT 24
Finished Aug 15 05:56:08 PM PDT 24
Peak memory 221768 kb
Host smart-65c85bbe-402d-4c15-a52a-70da4611687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754581527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3754581527 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3827488140
Short name T558
Test name
Test status
Simulation time 315202867654 ps
CPU time 4124.73 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 07:04:51 PM PDT 24
Peak memory 3322948 kb
Host smart-0589e6f6-f266-41f9-9369-cf85f42dd75d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827488140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3827488140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3133004324
Short name T180
Test name
Test status
Simulation time 61465361106 ps
CPU time 464.54 seconds
Started Aug 15 05:56:17 PM PDT 24
Finished Aug 15 06:04:02 PM PDT 24
Peak memory 637492 kb
Host smart-a0f172ae-89b7-4c2c-9982-e9590949b2e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133004324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3133004324 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.671191473
Short name T384
Test name
Test status
Simulation time 6855849259 ps
CPU time 30.64 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:46 PM PDT 24
Peak memory 221580 kb
Host smart-0b5b9c99-4177-4424-976d-7fcfa0f8655a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671191473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.671191473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.2202563901
Short name T700
Test name
Test status
Simulation time 36016088094 ps
CPU time 187.53 seconds
Started Aug 15 05:56:04 PM PDT 24
Finished Aug 15 05:59:12 PM PDT 24
Peak memory 414564 kb
Host smart-3b35f6c0-a354-445a-87f8-64ad5ee4e422
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2202563901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2202563901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_alert_test.894034203
Short name T421
Test name
Test status
Simulation time 58112289 ps
CPU time 0.8 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:56:22 PM PDT 24
Peak memory 203844 kb
Host smart-c193c209-63fc-43d5-b73a-e118330f6f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894034203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.894034203 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.735286472
Short name T403
Test name
Test status
Simulation time 7206820582 ps
CPU time 103.15 seconds
Started Aug 15 05:56:03 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 310320 kb
Host smart-f4652a8b-21ac-4976-89fa-3ac089563ac2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735286472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.735286472 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.1830098068
Short name T85
Test name
Test status
Simulation time 26774723837 ps
CPU time 509.12 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 06:04:45 PM PDT 24
Peak memory 242104 kb
Host smart-77d6ed6e-e748-49fe-9a0c-8b7093fa2e7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830098068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.183009806
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.300401382
Short name T252
Test name
Test status
Simulation time 1812330152 ps
CPU time 23.46 seconds
Started Aug 15 05:56:14 PM PDT 24
Finished Aug 15 05:56:37 PM PDT 24
Peak memory 219460 kb
Host smart-585c8ad8-b053-4a12-a338-890de81bca77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=300401382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.300401382 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2147309046
Short name T383
Test name
Test status
Simulation time 2272263165 ps
CPU time 24.09 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:56:30 PM PDT 24
Peak memory 215564 kb
Host smart-bc1ab23a-cd37-475c-922e-baa10fc8d9a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2147309046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2147309046 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.3168783456
Short name T660
Test name
Test status
Simulation time 29724436804 ps
CPU time 315.21 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 06:01:15 PM PDT 24
Peak memory 470448 kb
Host smart-1b2a5601-b252-4ce6-8bd0-25c1a38d308a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168783456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3
168783456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.2679589436
Short name T566
Test name
Test status
Simulation time 8561592713 ps
CPU time 361.44 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 06:02:11 PM PDT 24
Peak memory 368076 kb
Host smart-6cf23469-bc10-4ece-b2ae-a82c7279c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679589436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2679589436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.1603114966
Short name T476
Test name
Test status
Simulation time 1460532928 ps
CPU time 3.93 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 05:56:29 PM PDT 24
Peak memory 217548 kb
Host smart-e19f9ac6-483f-4bb2-97bf-f10262d8383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603114966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1603114966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.1189189221
Short name T668
Test name
Test status
Simulation time 142360906 ps
CPU time 1.31 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 218772 kb
Host smart-116134f0-08b6-4345-adaa-ccddbe95eb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189189221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1189189221 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.1947562618
Short name T311
Test name
Test status
Simulation time 20486202824 ps
CPU time 1190.65 seconds
Started Aug 15 05:56:17 PM PDT 24
Finished Aug 15 06:16:08 PM PDT 24
Peak memory 934276 kb
Host smart-6224f6b1-c5f1-43b0-8687-0bdf0aeb03e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947562618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.1947562618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.3831054079
Short name T547
Test name
Test status
Simulation time 17313546211 ps
CPU time 102.77 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:58:02 PM PDT 24
Peak memory 321708 kb
Host smart-00c720ef-707e-4263-80b0-64a8e56ae149
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831054079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3831054079 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.4027568793
Short name T555
Test name
Test status
Simulation time 7110428110 ps
CPU time 30.71 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:56:52 PM PDT 24
Peak memory 223600 kb
Host smart-0aaea6c2-2b66-40a3-adc8-6db76272d89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027568793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.4027568793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.3392299694
Short name T338
Test name
Test status
Simulation time 160553783977 ps
CPU time 868.64 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 06:10:35 PM PDT 24
Peak memory 973184 kb
Host smart-80dbd792-3166-4139-943c-e1a00f27dc5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3392299694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3392299694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_alert_test.726335229
Short name T630
Test name
Test status
Simulation time 32311101 ps
CPU time 0.76 seconds
Started Aug 15 05:56:22 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 204904 kb
Host smart-bd21d05a-f7ca-496c-8d04-f17123003e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726335229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.726335229 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.1956825557
Short name T195
Test name
Test status
Simulation time 10056016160 ps
CPU time 123.25 seconds
Started Aug 15 05:56:05 PM PDT 24
Finished Aug 15 05:58:09 PM PDT 24
Peak memory 325188 kb
Host smart-04c70937-11b9-4a9e-97a5-8de2bdacd5fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956825557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1956825557 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.3358643405
Short name T213
Test name
Test status
Simulation time 700220526 ps
CPU time 13.09 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 222464 kb
Host smart-ce4172e6-2a42-46d0-b8b2-194f5bf66ab5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3358643405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3358643405 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.915376535
Short name T714
Test name
Test status
Simulation time 3469313383 ps
CPU time 21.97 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 05:56:33 PM PDT 24
Peak memory 224484 kb
Host smart-9bc07437-079b-4976-8ec2-47dd3147d603
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=915376535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.915376535 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.3404152510
Short name T455
Test name
Test status
Simulation time 20101304525 ps
CPU time 389.43 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 06:02:50 PM PDT 24
Peak memory 538088 kb
Host smart-656cea3c-40f7-4f8e-b1db-ef2f69e9e748
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404152510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3
404152510 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_key_error.2045614243
Short name T581
Test name
Test status
Simulation time 2711326634 ps
CPU time 8.03 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 217780 kb
Host smart-3a44f756-2f3f-4f9e-8a34-111f9b78f5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045614243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2045614243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3551655940
Short name T446
Test name
Test status
Simulation time 41190939 ps
CPU time 1.22 seconds
Started Aug 15 05:56:05 PM PDT 24
Finished Aug 15 05:56:07 PM PDT 24
Peak memory 218988 kb
Host smart-1d5e84d2-507f-4a3e-b175-80d471ebaafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551655940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3551655940 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.4258369468
Short name T273
Test name
Test status
Simulation time 17905096045 ps
CPU time 1932.21 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 06:28:34 PM PDT 24
Peak memory 1345160 kb
Host smart-5d019e27-db5c-4bd2-bac0-b77ee38b5a0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258369468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.4258369468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.4260973545
Short name T456
Test name
Test status
Simulation time 12899638478 ps
CPU time 398.92 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 562356 kb
Host smart-f36b9e63-a5ba-41cd-8d5b-a033a375fb74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260973545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.4260973545 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.3642273410
Short name T614
Test name
Test status
Simulation time 223934707 ps
CPU time 5.31 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 218004 kb
Host smart-b2c63333-8824-4d8c-8e3a-f36ab997ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642273410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3642273410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.2778980448
Short name T390
Test name
Test status
Simulation time 14749831153 ps
CPU time 166.34 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 05:59:07 PM PDT 24
Peak memory 286688 kb
Host smart-d499978b-137b-498b-9a16-d31740531a8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2778980448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2778980448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2448548360
Short name T369
Test name
Test status
Simulation time 41757063 ps
CPU time 0.76 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:09 PM PDT 24
Peak memory 204964 kb
Host smart-bfb5ed08-bb8c-45c1-bd6b-b50b54cf76ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448548360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2448548360 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.1662935685
Short name T293
Test name
Test status
Simulation time 17604774865 ps
CPU time 35.94 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 05:56:48 PM PDT 24
Peak memory 241868 kb
Host smart-0218fb3a-00ba-4f0e-8752-968521b830aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662935685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1662935685 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2889706716
Short name T569
Test name
Test status
Simulation time 2153930749 ps
CPU time 116.94 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:58:18 PM PDT 24
Peak memory 224364 kb
Host smart-f4026d84-b851-4431-8f92-a452aec7790f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889706716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.288970671
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1049410941
Short name T278
Test name
Test status
Simulation time 110110894 ps
CPU time 8.32 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 220060 kb
Host smart-2d46696e-bcb7-4b92-b198-53745f794807
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1049410941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1049410941 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.266505700
Short name T84
Test name
Test status
Simulation time 137446478 ps
CPU time 3.69 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:12 PM PDT 24
Peak memory 215444 kb
Host smart-36cf5ad2-5702-480c-bfd4-cd0b4db5ad1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=266505700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.266505700 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.3081633577
Short name T508
Test name
Test status
Simulation time 55182640387 ps
CPU time 356.69 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 06:02:20 PM PDT 24
Peak memory 513272 kb
Host smart-46387eeb-7ecf-4aec-a29a-3cc66292756e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081633577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3
081633577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.761772240
Short name T334
Test name
Test status
Simulation time 26950419269 ps
CPU time 325.57 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 370920 kb
Host smart-58745d9a-db86-4b7a-bc29-4fdefa055de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761772240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.761772240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.1423324821
Short name T626
Test name
Test status
Simulation time 118910680 ps
CPU time 1.24 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 219084 kb
Host smart-d4d5d5e0-5056-498a-8cc8-59e6bf669233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423324821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1423324821 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.38602815
Short name T239
Test name
Test status
Simulation time 60281992514 ps
CPU time 3318.89 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 06:51:43 PM PDT 24
Peak memory 2995276 kb
Host smart-a713af0e-93be-44df-b05e-bb8e98df85da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and
_output.38602815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.1717123458
Short name T367
Test name
Test status
Simulation time 118458217079 ps
CPU time 428.52 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 06:03:27 PM PDT 24
Peak memory 579808 kb
Host smart-84dda7c0-44df-41e9-96c1-cbae00ec1e86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717123458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1717123458 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.3229853450
Short name T372
Test name
Test status
Simulation time 1404394834 ps
CPU time 32.54 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:48 PM PDT 24
Peak memory 217696 kb
Host smart-b2834f04-268c-4246-b24f-37fc239db113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229853450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3229853450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.797755670
Short name T419
Test name
Test status
Simulation time 54613396202 ps
CPU time 676 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 413712 kb
Host smart-a79188d9-2e36-4685-a62c-139f3bc21431
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=797755670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.797755670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_alert_test.1048996665
Short name T530
Test name
Test status
Simulation time 18231333 ps
CPU time 0.84 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 05:56:08 PM PDT 24
Peak memory 204944 kb
Host smart-533e3b00-d27f-4c3c-84a0-ff76a06371ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048996665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1048996665 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.2012884736
Short name T177
Test name
Test status
Simulation time 10731761692 ps
CPU time 288.33 seconds
Started Aug 15 05:56:05 PM PDT 24
Finished Aug 15 06:00:54 PM PDT 24
Peak memory 460060 kb
Host smart-20b538e9-10a1-4461-9866-c7f1f4983f9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012884736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2012884736 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3806068608
Short name T454
Test name
Test status
Simulation time 7599063917 ps
CPU time 238.69 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 06:00:24 PM PDT 24
Peak memory 232384 kb
Host smart-cb579d62-4c24-45a0-a979-3ab45e28b11b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806068608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.380606860
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.3213052468
Short name T425
Test name
Test status
Simulation time 672206157 ps
CPU time 11.49 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 05:56:30 PM PDT 24
Peak memory 221084 kb
Host smart-0d0b3fdf-4a6c-4866-a259-41d6b961d100
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3213052468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3213052468 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.1301750956
Short name T610
Test name
Test status
Simulation time 1876552160 ps
CPU time 37.58 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:56:56 PM PDT 24
Peak memory 223552 kb
Host smart-ae0d19aa-d9c3-40e1-9aff-42aa716a024d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1301750956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1301750956 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2202654105
Short name T26
Test name
Test status
Simulation time 18029215448 ps
CPU time 139.06 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:58:25 PM PDT 24
Peak memory 276780 kb
Host smart-25dd523e-ee52-464b-90ea-ad974e27239a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202654105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2
202654105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1842047126
Short name T683
Test name
Test status
Simulation time 12242852365 ps
CPU time 269.72 seconds
Started Aug 15 05:56:05 PM PDT 24
Finished Aug 15 06:00:35 PM PDT 24
Peak memory 496904 kb
Host smart-4b569f58-7def-4c59-b64b-4a3c8d3630c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842047126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1842047126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.4278767057
Short name T485
Test name
Test status
Simulation time 656375617 ps
CPU time 1.27 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 217476 kb
Host smart-98c59eb0-e674-44d4-abe4-e631609e0fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278767057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.4278767057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.2787044598
Short name T649
Test name
Test status
Simulation time 51256509 ps
CPU time 1.08 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:56:08 PM PDT 24
Peak memory 223316 kb
Host smart-1d395932-4cec-43b7-9e32-2501eb6eed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787044598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2787044598 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2593132957
Short name T616
Test name
Test status
Simulation time 109339359118 ps
CPU time 3079.15 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 06:47:34 PM PDT 24
Peak memory 1810096 kb
Host smart-424e4237-9cc7-4b09-929f-9f96b4d8360b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593132957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2593132957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.1497822779
Short name T289
Test name
Test status
Simulation time 11987924204 ps
CPU time 353.13 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 06:02:12 PM PDT 24
Peak memory 532808 kb
Host smart-3da01d74-ea9f-49a4-9e15-96bd40cd806c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497822779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1497822779 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.2728269105
Short name T492
Test name
Test status
Simulation time 4828073039 ps
CPU time 33.29 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 05:56:51 PM PDT 24
Peak memory 217788 kb
Host smart-2a3e2c49-a8b6-47b9-b0b5-9c9cf32620b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728269105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2728269105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.3221032177
Short name T281
Test name
Test status
Simulation time 57300451115 ps
CPU time 478.77 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 06:04:17 PM PDT 24
Peak memory 298540 kb
Host smart-a846ef6c-ca41-46c9-a91a-ad44c4ac0d9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3221032177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3221032177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3542839553
Short name T203
Test name
Test status
Simulation time 17557577 ps
CPU time 0.77 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:56:07 PM PDT 24
Peak memory 204920 kb
Host smart-2c353cf5-5efe-4e8a-8fc0-308a5e2f31e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542839553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3542839553 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.1674530416
Short name T429
Test name
Test status
Simulation time 10697601461 ps
CPU time 102.76 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:58:07 PM PDT 24
Peak memory 267008 kb
Host smart-2aadfa4a-fc25-46c2-b474-15bdf9c1894e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674530416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1674530416 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.1787973015
Short name T305
Test name
Test status
Simulation time 7586199939 ps
CPU time 183.76 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:59:23 PM PDT 24
Peak memory 226956 kb
Host smart-833b03d9-dc6e-4996-9a92-e71b7fbfcfbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787973015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.178797301
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.4025487358
Short name T405
Test name
Test status
Simulation time 289332938 ps
CPU time 4.36 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 05:56:12 PM PDT 24
Peak memory 223596 kb
Host smart-485b6349-81f7-48b9-bdbd-d7729a955560
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025487358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.4025487358 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.3912408442
Short name T584
Test name
Test status
Simulation time 294377524 ps
CPU time 22.97 seconds
Started Aug 15 05:56:13 PM PDT 24
Finished Aug 15 05:56:36 PM PDT 24
Peak memory 220528 kb
Host smart-c43d939d-01d8-44f5-bf36-71b91e12f2ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3912408442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3912408442 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3870063052
Short name T709
Test name
Test status
Simulation time 15771980008 ps
CPU time 319.96 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 06:01:31 PM PDT 24
Peak memory 351104 kb
Host smart-c495dd87-48f6-4266-8f7f-6af444bb7f22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870063052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3
870063052 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.777324537
Short name T158
Test name
Test status
Simulation time 7133569393 ps
CPU time 200.24 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 05:59:31 PM PDT 24
Peak memory 420272 kb
Host smart-304ce085-9818-41dc-90a3-1ac25808014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777324537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.777324537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.1628996197
Short name T61
Test name
Test status
Simulation time 2147139800 ps
CPU time 6.01 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 05:56:15 PM PDT 24
Peak memory 217624 kb
Host smart-f5690e87-3012-4d21-8775-c7c54d804a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628996197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1628996197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.2383446894
Short name T622
Test name
Test status
Simulation time 4197223556 ps
CPU time 47.71 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:57:09 PM PDT 24
Peak memory 245780 kb
Host smart-c3f68195-99e8-4d70-9726-79b0e4865fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383446894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2383446894 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_sideload.3322926540
Short name T72
Test name
Test status
Simulation time 8953850823 ps
CPU time 196.06 seconds
Started Aug 15 05:56:22 PM PDT 24
Finished Aug 15 05:59:38 PM PDT 24
Peak memory 309068 kb
Host smart-0630d0f2-52d5-48d1-917b-7c8e07efe4c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322926540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3322926540 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.461603785
Short name T297
Test name
Test status
Simulation time 1646236641 ps
CPU time 23.72 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 05:56:44 PM PDT 24
Peak memory 217468 kb
Host smart-f7be5f73-7e08-44a7-97a4-e66572264786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461603785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.461603785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.467026382
Short name T422
Test name
Test status
Simulation time 199071134401 ps
CPU time 1491.41 seconds
Started Aug 15 05:56:13 PM PDT 24
Finished Aug 15 06:21:05 PM PDT 24
Peak memory 813340 kb
Host smart-45fa0fef-5e74-4ba1-b8a4-c61666ac20b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=467026382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.467026382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2455942725
Short name T592
Test name
Test status
Simulation time 44421453 ps
CPU time 0.77 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 204904 kb
Host smart-beedd9a2-f77d-445a-9001-6222cd453ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455942725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2455942725 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.1287662085
Short name T109
Test name
Test status
Simulation time 23656454629 ps
CPU time 143.52 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 05:58:34 PM PDT 24
Peak memory 283424 kb
Host smart-2c37ec62-031f-4272-bf3b-6c7fdac7fc59
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287662085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1287662085 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2153640220
Short name T71
Test name
Test status
Simulation time 94287133053 ps
CPU time 787.52 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 06:09:19 PM PDT 24
Peak memory 252928 kb
Host smart-fb03a823-bf9a-4912-af91-da34b3f73d32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153640220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.215364022
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3014454158
Short name T201
Test name
Test status
Simulation time 179635820 ps
CPU time 3.44 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 216336 kb
Host smart-6c383697-4e77-4c94-9695-1e2858a4cd6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3014454158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3014454158 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.18777696
Short name T505
Test name
Test status
Simulation time 241104964 ps
CPU time 19.05 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:34 PM PDT 24
Peak memory 222400 kb
Host smart-52341de5-ebb4-42e5-8761-30601f8352a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=18777696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.18777696 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.1466874756
Short name T631
Test name
Test status
Simulation time 5202214492 ps
CPU time 152.94 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 05:58:43 PM PDT 24
Peak memory 282160 kb
Host smart-f8f2683f-52ad-446e-89b9-2aff5716dc12
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466874756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1
466874756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.4168983058
Short name T30
Test name
Test status
Simulation time 19078335376 ps
CPU time 271.09 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 06:00:39 PM PDT 24
Peak memory 475576 kb
Host smart-a5f0ae00-5109-4dc2-9212-42195700b767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168983058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.4168983058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.2606277362
Short name T662
Test name
Test status
Simulation time 2123773709 ps
CPU time 3.44 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:18 PM PDT 24
Peak memory 217552 kb
Host smart-885a56a9-833a-43b7-8a08-2871f486d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606277362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2606277362 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.1898911002
Short name T222
Test name
Test status
Simulation time 8686692275 ps
CPU time 390.7 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 06:02:50 PM PDT 24
Peak memory 485616 kb
Host smart-f2a895ad-7b88-4d9b-b3ed-8a02f7d17c8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898911002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.1898911002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.3291112889
Short name T597
Test name
Test status
Simulation time 14164800206 ps
CPU time 371.87 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 550468 kb
Host smart-0f49766a-1465-49cb-b68a-aca7fcb52b5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291112889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3291112889 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.787565751
Short name T182
Test name
Test status
Simulation time 247497718 ps
CPU time 6.06 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 05:56:16 PM PDT 24
Peak memory 218800 kb
Host smart-b3de0e29-69ad-4c14-92d0-010624e0d9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787565751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.787565751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.142207523
Short name T580
Test name
Test status
Simulation time 67384944447 ps
CPU time 1690.62 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 06:24:22 PM PDT 24
Peak memory 1305736 kb
Host smart-4595ff7d-09ca-42d5-9dd7-334774e80cba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=142207523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.142207523 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_alert_test.4072208367
Short name T230
Test name
Test status
Simulation time 42114451 ps
CPU time 0.87 seconds
Started Aug 15 05:55:30 PM PDT 24
Finished Aug 15 05:55:31 PM PDT 24
Peak memory 204952 kb
Host smart-71824e7f-253c-4621-b4c5-9cd29928ec53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072208367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.4072208367 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.3577331099
Short name T160
Test name
Test status
Simulation time 42667688290 ps
CPU time 257.21 seconds
Started Aug 15 05:55:35 PM PDT 24
Finished Aug 15 05:59:52 PM PDT 24
Peak memory 425172 kb
Host smart-fd1b74db-d649-4abe-b322-0a858fa70a03
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577331099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3577331099 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.4248321848
Short name T499
Test name
Test status
Simulation time 11668552406 ps
CPU time 151.96 seconds
Started Aug 15 05:55:58 PM PDT 24
Finished Aug 15 05:58:30 PM PDT 24
Peak memory 348080 kb
Host smart-d2fd1183-284b-4765-a9c2-a819396e8755
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248321848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.4248321848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2989737989
Short name T267
Test name
Test status
Simulation time 1660406660 ps
CPU time 38.98 seconds
Started Aug 15 05:55:34 PM PDT 24
Finished Aug 15 05:56:13 PM PDT 24
Peak memory 219896 kb
Host smart-64bf57fd-e5b7-434a-b52b-4dc411a397ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989737989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2989737989
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.2227233309
Short name T656
Test name
Test status
Simulation time 1171788992 ps
CPU time 32.57 seconds
Started Aug 15 05:55:57 PM PDT 24
Finished Aug 15 05:56:30 PM PDT 24
Peak memory 223512 kb
Host smart-a375599c-6c7e-4e2a-9b79-3ab2cbfb0fc8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2227233309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2227233309 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.2046624753
Short name T575
Test name
Test status
Simulation time 1178874139 ps
CPU time 18.63 seconds
Started Aug 15 05:55:26 PM PDT 24
Finished Aug 15 05:55:45 PM PDT 24
Peak memory 223528 kb
Host smart-7046bb12-b6b7-440a-864b-8df8b6ef4f0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2046624753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2046624753 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.4058685410
Short name T625
Test name
Test status
Simulation time 1197121842 ps
CPU time 10.69 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 05:55:40 PM PDT 24
Peak memory 218120 kb
Host smart-3726aeab-a7df-4845-bf4d-548d5784617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058685410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.4058685410 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.2421904226
Short name T336
Test name
Test status
Simulation time 24216179849 ps
CPU time 231.86 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:59:24 PM PDT 24
Peak memory 427540 kb
Host smart-db3237f5-b235-4b66-a862-b850ce434f1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421904226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.24
21904226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.1249715432
Short name T609
Test name
Test status
Simulation time 28525985682 ps
CPU time 132.96 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 05:57:41 PM PDT 24
Peak memory 345804 kb
Host smart-24aa0cac-2895-4cf1-932d-b9709d9f297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249715432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1249715432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.1301261991
Short name T58
Test name
Test status
Simulation time 2650128713 ps
CPU time 4.2 seconds
Started Aug 15 05:55:56 PM PDT 24
Finished Aug 15 05:56:00 PM PDT 24
Peak memory 217912 kb
Host smart-313a2e48-779b-4226-924b-7ffbf25d78ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301261991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1301261991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.1229102122
Short name T544
Test name
Test status
Simulation time 46001154 ps
CPU time 1.36 seconds
Started Aug 15 05:55:26 PM PDT 24
Finished Aug 15 05:55:27 PM PDT 24
Peak memory 217016 kb
Host smart-4b3cacc4-22fb-498d-9642-93b1398023dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229102122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1229102122 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.3711636576
Short name T381
Test name
Test status
Simulation time 118198788856 ps
CPU time 1802.88 seconds
Started Aug 15 05:55:27 PM PDT 24
Finished Aug 15 06:25:30 PM PDT 24
Peak memory 1249836 kb
Host smart-11d12100-03ee-4ff7-8fd7-73536aba07e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711636576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.3711636576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.4115965227
Short name T457
Test name
Test status
Simulation time 20716733492 ps
CPU time 133.31 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:57:45 PM PDT 24
Peak memory 339532 kb
Host smart-51aa9167-fd6a-4b4f-a553-7874364fe17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115965227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.4115965227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.424498801
Short name T10
Test name
Test status
Simulation time 10673182297 ps
CPU time 33.96 seconds
Started Aug 15 05:55:40 PM PDT 24
Finished Aug 15 05:56:14 PM PDT 24
Peak memory 242488 kb
Host smart-377edca5-94fe-41d0-a87b-c0c373f7e54b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424498801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.424498801 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.194592631
Short name T514
Test name
Test status
Simulation time 6825066992 ps
CPU time 150.94 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 05:57:59 PM PDT 24
Peak memory 286324 kb
Host smart-ee7b22d6-ca86-4327-86a1-5bef8786c79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194592631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.194592631 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3744293380
Short name T218
Test name
Test status
Simulation time 607904212 ps
CPU time 30.7 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:56:03 PM PDT 24
Peak memory 222156 kb
Host smart-c23755f4-0f37-4679-80c2-fc19b70a060f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744293380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3744293380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2171025022
Short name T589
Test name
Test status
Simulation time 37394642161 ps
CPU time 709.75 seconds
Started Aug 15 05:55:53 PM PDT 24
Finished Aug 15 06:07:48 PM PDT 24
Peak memory 969064 kb
Host smart-e275066f-f3a7-4bd9-a10f-d069d538e2c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2171025022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2171025022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.2911349728
Short name T359
Test name
Test status
Simulation time 264765547 ps
CPU time 2.39 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:55:34 PM PDT 24
Peak memory 217896 kb
Host smart-3673b7db-5c1c-4f34-884e-3af95e5a2f3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911349728 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.2911349728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1006261077
Short name T613
Test name
Test status
Simulation time 72182304 ps
CPU time 2.08 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 05:55:30 PM PDT 24
Peak memory 217616 kb
Host smart-3cc0350d-4925-4277-9d8d-b9cc57be23af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006261077 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1006261077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.3927186318
Short name T459
Test name
Test status
Simulation time 33788832215 ps
CPU time 1752.65 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 06:24:45 PM PDT 24
Peak memory 1189800 kb
Host smart-07167fb5-76bf-4c76-94d0-e7f8c96adbdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3927186318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3927186318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.1604192025
Short name T538
Test name
Test status
Simulation time 2301341123 ps
CPU time 34.57 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:56:07 PM PDT 24
Peak memory 218880 kb
Host smart-b7eee374-03d1-4801-bc96-d5579af978fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1604192025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1604192025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.1381810604
Short name T603
Test name
Test status
Simulation time 273758258224 ps
CPU time 2315.36 seconds
Started Aug 15 05:55:35 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 2308608 kb
Host smart-f7562a0c-026b-43cf-ae4c-ba2c18460134
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1381810604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1381810604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1064766336
Short name T276
Test name
Test status
Simulation time 205796875464 ps
CPU time 1504.69 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 06:20:33 PM PDT 24
Peak memory 1723248 kb
Host smart-158dbad9-f910-493b-9df7-9af040c257f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1064766336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1064766336 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.186740607
Short name T181
Test name
Test status
Simulation time 92284264350 ps
CPU time 2216.08 seconds
Started Aug 15 05:55:27 PM PDT 24
Finished Aug 15 06:32:24 PM PDT 24
Peak memory 1317612 kb
Host smart-fc58b3a3-fe82-4d0c-b9fd-e69075a27bac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=186740607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.186740607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.2337876472
Short name T251
Test name
Test status
Simulation time 63556561717 ps
CPU time 2836.34 seconds
Started Aug 15 05:55:27 PM PDT 24
Finished Aug 15 06:42:44 PM PDT 24
Peak memory 3075560 kb
Host smart-cd9d8f6d-edc3-4256-9eac-877ff8657f74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2337876472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2337876472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3903231732
Short name T579
Test name
Test status
Simulation time 16444153 ps
CPU time 0.81 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 05:56:26 PM PDT 24
Peak memory 204936 kb
Host smart-e1d337ad-9dc4-4c33-a04b-dc81ee100969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903231732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3903231732 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.1599197877
Short name T503
Test name
Test status
Simulation time 1661734199 ps
CPU time 95.37 seconds
Started Aug 15 05:56:13 PM PDT 24
Finished Aug 15 05:57:49 PM PDT 24
Peak memory 263272 kb
Host smart-cd181410-ecf2-4850-a57b-0c5ac2f4d8b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599197877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1599197877 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2829461043
Short name T172
Test name
Test status
Simulation time 5869415981 ps
CPU time 537.24 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 06:05:20 PM PDT 24
Peak memory 236076 kb
Host smart-a41aa29a-f0e6-47e2-97c4-b99165279069
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829461043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.282946104
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.2131921266
Short name T447
Test name
Test status
Simulation time 5467401983 ps
CPU time 121.75 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 05:58:26 PM PDT 24
Peak memory 264780 kb
Host smart-0288d6ab-8ecc-4501-9578-750ced37404e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131921266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2
131921266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.136753799
Short name T526
Test name
Test status
Simulation time 70758488790 ps
CPU time 394.47 seconds
Started Aug 15 05:56:29 PM PDT 24
Finished Aug 15 06:03:03 PM PDT 24
Peak memory 591268 kb
Host smart-c7b35b34-3a73-49e8-9687-7d019315f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136753799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.136753799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.656653823
Short name T484
Test name
Test status
Simulation time 822396772 ps
CPU time 4.35 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 217232 kb
Host smart-d5330527-df7c-4d9f-ab50-1342061f1b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656653823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.656653823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.1978108526
Short name T54
Test name
Test status
Simulation time 61456495 ps
CPU time 1.46 seconds
Started Aug 15 05:56:31 PM PDT 24
Finished Aug 15 05:56:33 PM PDT 24
Peak memory 218724 kb
Host smart-31b03956-9bba-4a0e-a264-b2bc2e6acecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978108526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1978108526 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3923493481
Short name T382
Test name
Test status
Simulation time 5068949907 ps
CPU time 168.99 seconds
Started Aug 15 05:56:13 PM PDT 24
Finished Aug 15 05:59:02 PM PDT 24
Peak memory 451904 kb
Host smart-370ab536-e179-4034-9154-c2d8f77d117b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923493481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3923493481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.2415163393
Short name T585
Test name
Test status
Simulation time 27402964624 ps
CPU time 303.38 seconds
Started Aug 15 05:56:17 PM PDT 24
Finished Aug 15 06:01:20 PM PDT 24
Peak memory 497988 kb
Host smart-feb8aa8b-b6e5-43aa-bae5-0441c4b8a86c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415163393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2415163393 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.3574087602
Short name T632
Test name
Test status
Simulation time 484747796 ps
CPU time 26.53 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 05:56:44 PM PDT 24
Peak memory 217956 kb
Host smart-07848bbc-0c25-435b-9edb-6557fabc2211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574087602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3574087602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_alert_test.2217877840
Short name T687
Test name
Test status
Simulation time 28875708 ps
CPU time 0.83 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 204928 kb
Host smart-e9e332a0-bc97-4a9f-b92a-cd1d1cb2433b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217877840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2217877840 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.3264912282
Short name T605
Test name
Test status
Simulation time 6002098167 ps
CPU time 107.38 seconds
Started Aug 15 05:56:17 PM PDT 24
Finished Aug 15 05:58:05 PM PDT 24
Peak memory 262716 kb
Host smart-b5459932-f381-454f-9e3c-fdf9a787ac42
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264912282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3264912282 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.2063786262
Short name T426
Test name
Test status
Simulation time 21099719520 ps
CPU time 377.85 seconds
Started Aug 15 05:56:13 PM PDT 24
Finished Aug 15 06:02:31 PM PDT 24
Peak memory 237364 kb
Host smart-44c8186b-5724-4fd1-ab6b-38f440ab3746
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063786262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.206378626
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.1887839706
Short name T525
Test name
Test status
Simulation time 6643630423 ps
CPU time 112.97 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:58:08 PM PDT 24
Peak memory 315408 kb
Host smart-c6091340-4988-4174-af80-dacc229c6049
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887839706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1
887839706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.1337733982
Short name T227
Test name
Test status
Simulation time 70057112566 ps
CPU time 252.18 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 06:00:32 PM PDT 24
Peak memory 454640 kb
Host smart-92573283-205d-42af-9361-ded73869faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337733982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1337733982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2899179041
Short name T420
Test name
Test status
Simulation time 105922859 ps
CPU time 1.16 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:16 PM PDT 24
Peak memory 217224 kb
Host smart-ed1535f3-bfda-4e30-be72-64e3c082f976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899179041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2899179041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.3624097150
Short name T535
Test name
Test status
Simulation time 67435944 ps
CPU time 1.22 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 218680 kb
Host smart-eafe7131-1c77-469c-9c79-82f37df63589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624097150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3624097150 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.425123477
Short name T606
Test name
Test status
Simulation time 146516019878 ps
CPU time 4860.17 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 07:17:21 PM PDT 24
Peak memory 3611152 kb
Host smart-298fc071-e373-454a-b5f5-c1e5a3f4c7c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425123477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_an
d_output.425123477 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.2135764417
Short name T708
Test name
Test status
Simulation time 3117291241 ps
CPU time 247.79 seconds
Started Aug 15 05:56:22 PM PDT 24
Finished Aug 15 06:00:30 PM PDT 24
Peak memory 327052 kb
Host smart-bcbfdfd4-3bb0-4068-af1d-b512bc74ea55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135764417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2135764417 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.3423780439
Short name T249
Test name
Test status
Simulation time 2438013100 ps
CPU time 24.04 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 05:56:40 PM PDT 24
Peak memory 218036 kb
Host smart-0ba59d7c-565f-4150-827b-199c710a670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423780439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3423780439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3988530148
Short name T563
Test name
Test status
Simulation time 1999447518 ps
CPU time 23.03 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:56:44 PM PDT 24
Peak memory 232932 kb
Host smart-ca2b99ef-7ed0-49e4-a060-df12a32f6c4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3988530148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3988530148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_alert_test.1022590893
Short name T600
Test name
Test status
Simulation time 24873674 ps
CPU time 0.82 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 204928 kb
Host smart-cf5521af-5603-4358-b79e-843c59ad42f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022590893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1022590893 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.1226365396
Short name T493
Test name
Test status
Simulation time 2915654172 ps
CPU time 72.42 seconds
Started Aug 15 05:56:22 PM PDT 24
Finished Aug 15 05:57:34 PM PDT 24
Peak memory 281552 kb
Host smart-e27c61d1-0bbc-4844-8e4d-de16e8f7c224
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226365396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1226365396 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1913164672
Short name T517
Test name
Test status
Simulation time 18490937834 ps
CPU time 294.3 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 06:01:14 PM PDT 24
Peak memory 232344 kb
Host smart-edad3745-298f-47fb-af45-3ee2aab32353
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913164672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.191316467
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.3033013317
Short name T534
Test name
Test status
Simulation time 11915978286 ps
CPU time 50 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 05:57:15 PM PDT 24
Peak memory 258016 kb
Host smart-902aaa0e-3557-4b03-8064-6a5029431bdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033013317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3
033013317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2228240708
Short name T713
Test name
Test status
Simulation time 8253193097 ps
CPU time 331.3 seconds
Started Aug 15 05:56:14 PM PDT 24
Finished Aug 15 06:01:45 PM PDT 24
Peak memory 357404 kb
Host smart-a0811124-7fa9-4330-bc03-4b3ebe5f701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228240708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2228240708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.4063891093
Short name T331
Test name
Test status
Simulation time 1289587741 ps
CPU time 4.33 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:20 PM PDT 24
Peak memory 217684 kb
Host smart-12dcea33-a1d5-4b5d-ad37-46effeecfc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063891093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.4063891093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.421941564
Short name T570
Test name
Test status
Simulation time 174610996 ps
CPU time 1.45 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 216968 kb
Host smart-f9646555-3544-46d5-bae9-0fb203d3fba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421941564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.421941564 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.2571480847
Short name T223
Test name
Test status
Simulation time 37273662491 ps
CPU time 1438.52 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 06:20:20 PM PDT 24
Peak memory 1695824 kb
Host smart-4abac0de-7537-4c54-be66-e69cd6013b59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571480847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.2571480847 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2315982784
Short name T188
Test name
Test status
Simulation time 9472390612 ps
CPU time 105.51 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 05:58:10 PM PDT 24
Peak memory 261496 kb
Host smart-dff0fb61-b472-4620-a6d4-205a182b6e1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315982784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2315982784 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2265522890
Short name T255
Test name
Test status
Simulation time 2407466951 ps
CPU time 31.79 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 05:56:50 PM PDT 24
Peak memory 217896 kb
Host smart-8aaf6424-1ec3-45b2-b4c6-b4058ca4e367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265522890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2265522890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_alert_test.3184737838
Short name T682
Test name
Test status
Simulation time 42311445 ps
CPU time 0.76 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 204904 kb
Host smart-2735cc27-fa6f-4fdd-98d4-f0599cbdea04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184737838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3184737838 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.1084167086
Short name T541
Test name
Test status
Simulation time 3104134404 ps
CPU time 90.7 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 05:57:49 PM PDT 24
Peak memory 259900 kb
Host smart-a97a3e85-babb-4d1c-8ebc-2936acdc2a05
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084167086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1084167086 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.620666619
Short name T494
Test name
Test status
Simulation time 8336361238 ps
CPU time 703.05 seconds
Started Aug 15 05:56:14 PM PDT 24
Finished Aug 15 06:07:58 PM PDT 24
Peak memory 240624 kb
Host smart-9c0c051d-abe4-4915-b0c4-59842da022c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620666619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.620666619
+enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.3437891359
Short name T207
Test name
Test status
Simulation time 44940579065 ps
CPU time 244.35 seconds
Started Aug 15 05:56:18 PM PDT 24
Finished Aug 15 06:00:22 PM PDT 24
Peak memory 428088 kb
Host smart-1bfc99cb-e1d2-40de-89d1-2508f2b999f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437891359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3
437891359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.871393633
Short name T667
Test name
Test status
Simulation time 6722443896 ps
CPU time 103.57 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:58:05 PM PDT 24
Peak memory 314172 kb
Host smart-a995ba26-6a18-459c-9fde-9060feaa3a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871393633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.871393633 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.1760604827
Short name T17
Test name
Test status
Simulation time 904164472 ps
CPU time 4.79 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:56:20 PM PDT 24
Peak memory 217404 kb
Host smart-14d7ff13-8086-4807-b301-33b1273c857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760604827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1760604827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1362737264
Short name T444
Test name
Test status
Simulation time 52027486166 ps
CPU time 2220.71 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 2354708 kb
Host smart-64871479-3701-467e-9b05-b6215fbc3b3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362737264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1362737264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.3310128363
Short name T409
Test name
Test status
Simulation time 19166693319 ps
CPU time 120.26 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 05:58:15 PM PDT 24
Peak memory 325980 kb
Host smart-edacfa4e-3a70-485c-95f9-189b9e6a7cdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310128363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3310128363 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.2191905235
Short name T184
Test name
Test status
Simulation time 3484410432 ps
CPU time 50.49 seconds
Started Aug 15 05:56:14 PM PDT 24
Finished Aug 15 05:57:04 PM PDT 24
Peak memory 217952 kb
Host smart-5733b977-602e-47d6-acb2-a5cea3dc4fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191905235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2191905235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3693682520
Short name T340
Test name
Test status
Simulation time 2851665416 ps
CPU time 47.94 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:57:07 PM PDT 24
Peak memory 240552 kb
Host smart-f6ff4750-f7bd-4637-b87a-751ea67b6509
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3693682520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3693682520 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2449932060
Short name T211
Test name
Test status
Simulation time 45630540 ps
CPU time 0.81 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:56:22 PM PDT 24
Peak memory 204912 kb
Host smart-16e010de-2376-4b8e-96fd-b8087d29e41f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449932060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2449932060 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.2744849030
Short name T37
Test name
Test status
Simulation time 3331720361 ps
CPU time 155.55 seconds
Started Aug 15 05:56:12 PM PDT 24
Finished Aug 15 05:58:48 PM PDT 24
Peak memory 284620 kb
Host smart-3d415e52-4126-4b20-9305-fc2a3f88bf3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744849030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2744849030 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1226285955
Short name T40
Test name
Test status
Simulation time 28860500296 ps
CPU time 616.01 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 06:06:40 PM PDT 24
Peak memory 237676 kb
Host smart-0e0cd2a5-0e42-4495-80cc-0d0ddd585d58
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226285955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.122628595
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.4051622993
Short name T601
Test name
Test status
Simulation time 15750411837 ps
CPU time 71.94 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 245996 kb
Host smart-b69113f5-7d86-4d7d-a403-5811bcad1e20
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051622993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.4
051622993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_key_error.1348757689
Short name T397
Test name
Test status
Simulation time 3657778766 ps
CPU time 4.72 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:56:24 PM PDT 24
Peak memory 217716 kb
Host smart-73f20d5b-d08a-48db-b855-dcd8e67ce462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348757689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1348757689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.701917590
Short name T468
Test name
Test status
Simulation time 47939965 ps
CPU time 1.36 seconds
Started Aug 15 05:56:26 PM PDT 24
Finished Aug 15 05:56:28 PM PDT 24
Peak memory 216988 kb
Host smart-51f04295-b463-499f-b8e6-aecef86ff2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701917590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.701917590 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.1074775706
Short name T483
Test name
Test status
Simulation time 20868919279 ps
CPU time 2588.15 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 06:39:30 PM PDT 24
Peak memory 1542220 kb
Host smart-c1222c8e-7461-42cd-9c1b-86304a35e9e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074775706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.1074775706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.662934824
Short name T637
Test name
Test status
Simulation time 67445775492 ps
CPU time 438.07 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 06:03:42 PM PDT 24
Peak memory 595960 kb
Host smart-df29e7c6-f499-4ffa-8039-b0610d654ed8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662934824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.662934824 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.658309372
Short name T314
Test name
Test status
Simulation time 1695394968 ps
CPU time 16.47 seconds
Started Aug 15 05:56:19 PM PDT 24
Finished Aug 15 05:56:35 PM PDT 24
Peak memory 217980 kb
Host smart-b112bf41-dd1b-4bbd-8eae-1fadc47616cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658309372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.658309372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.4066924211
Short name T388
Test name
Test status
Simulation time 232699468368 ps
CPU time 1495.98 seconds
Started Aug 15 05:56:36 PM PDT 24
Finished Aug 15 06:21:32 PM PDT 24
Peak memory 1612544 kb
Host smart-6f7f0335-bbd3-4d31-9acf-05c4ed8a08da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4066924211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.4066924211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_alert_test.166374708
Short name T500
Test name
Test status
Simulation time 14138763 ps
CPU time 0.8 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 204932 kb
Host smart-ad40da0d-738d-4a36-a235-412e54f38793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166374708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.166374708 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.2439202228
Short name T298
Test name
Test status
Simulation time 25526866940 ps
CPU time 46.4 seconds
Started Aug 15 05:56:26 PM PDT 24
Finished Aug 15 05:57:13 PM PDT 24
Peak memory 250116 kb
Host smart-081278d0-ecd2-4ed9-8619-fa0f171693b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439202228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2439202228 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.2108700608
Short name T357
Test name
Test status
Simulation time 27023264345 ps
CPU time 988.45 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 06:12:53 PM PDT 24
Peak memory 258004 kb
Host smart-bfafd397-7a61-450d-9e10-7f56fb87c7dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108700608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.210870060
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.1246778533
Short name T477
Test name
Test status
Simulation time 116807241315 ps
CPU time 340.99 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 06:02:04 PM PDT 24
Peak memory 493720 kb
Host smart-1d7ce56d-c1ec-49ee-91bf-06dc8c8853b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246778533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1
246778533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.3899641882
Short name T242
Test name
Test status
Simulation time 18793651254 ps
CPU time 396.95 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 06:03:01 PM PDT 24
Peak memory 389836 kb
Host smart-c015ee6a-b0be-46cc-b917-0c1e176ab8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899641882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3899641882 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.807338396
Short name T391
Test name
Test status
Simulation time 794393487 ps
CPU time 2.47 seconds
Started Aug 15 05:56:21 PM PDT 24
Finished Aug 15 05:56:24 PM PDT 24
Peak memory 218556 kb
Host smart-dca230cd-54df-4b75-a9b3-e28e093914cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807338396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.807338396 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.190033940
Short name T88
Test name
Test status
Simulation time 43662298 ps
CPU time 1.22 seconds
Started Aug 15 05:56:26 PM PDT 24
Finished Aug 15 05:56:27 PM PDT 24
Peak memory 218668 kb
Host smart-60298bd8-087b-4ac7-9b58-7ccc4fc37ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190033940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.190033940 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.21419351
Short name T374
Test name
Test status
Simulation time 24167064826 ps
CPU time 332.36 seconds
Started Aug 15 05:56:27 PM PDT 24
Finished Aug 15 06:02:00 PM PDT 24
Peak memory 689272 kb
Host smart-343aec69-c017-4119-b9d2-b50930a60111
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21419351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and
_output.21419351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2340126778
Short name T189
Test name
Test status
Simulation time 12116654424 ps
CPU time 180.2 seconds
Started Aug 15 05:56:34 PM PDT 24
Finished Aug 15 05:59:34 PM PDT 24
Peak memory 295296 kb
Host smart-c68934d9-bcd9-4cc8-a7b9-15117e14d633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340126778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2340126778 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.679603338
Short name T275
Test name
Test status
Simulation time 8389210685 ps
CPU time 32.43 seconds
Started Aug 15 05:56:26 PM PDT 24
Finished Aug 15 05:56:59 PM PDT 24
Peak memory 218028 kb
Host smart-6573a09e-3246-4ca4-ac61-150fd9105988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679603338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.679603338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.4237819330
Short name T22
Test name
Test status
Simulation time 191792776388 ps
CPU time 724.83 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 06:08:30 PM PDT 24
Peak memory 851552 kb
Host smart-55c0354c-3b49-408c-ac0f-66914fc19e72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4237819330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.4237819330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_alert_test.2103008396
Short name T577
Test name
Test status
Simulation time 29143308 ps
CPU time 0.72 seconds
Started Aug 15 05:56:27 PM PDT 24
Finished Aug 15 05:56:28 PM PDT 24
Peak memory 204872 kb
Host smart-8992db29-f04c-42be-9134-51a915e3187e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103008396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2103008396 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.865260664
Short name T342
Test name
Test status
Simulation time 8884817322 ps
CPU time 155.58 seconds
Started Aug 15 05:56:27 PM PDT 24
Finished Aug 15 05:59:03 PM PDT 24
Peak memory 352740 kb
Host smart-ed75fa0a-ff92-4574-a033-015341f86457
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865260664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.865260664 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.1048762476
Short name T440
Test name
Test status
Simulation time 139031779523 ps
CPU time 821.55 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 06:10:06 PM PDT 24
Peak memory 252376 kb
Host smart-896542c2-00b4-4322-a892-8d9d7e04826f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048762476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.104876247
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.2504038898
Short name T105
Test name
Test status
Simulation time 16624977233 ps
CPU time 310.48 seconds
Started Aug 15 05:56:22 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 479596 kb
Host smart-aaea9db7-cad3-4a3d-8ecb-ec87db7a6b4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504038898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2
504038898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1915401145
Short name T161
Test name
Test status
Simulation time 10336927693 ps
CPU time 121.36 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 05:58:22 PM PDT 24
Peak memory 330256 kb
Host smart-ac87d022-30b6-4ddd-994d-9bd527b8a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915401145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1915401145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.612733462
Short name T574
Test name
Test status
Simulation time 3661870530 ps
CPU time 3.64 seconds
Started Aug 15 05:56:36 PM PDT 24
Finished Aug 15 05:56:40 PM PDT 24
Peak memory 217620 kb
Host smart-3d42f35b-2036-4313-8a3e-293534a5b382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612733462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.612733462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.777712998
Short name T87
Test name
Test status
Simulation time 51202758 ps
CPU time 1.36 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 05:56:26 PM PDT 24
Peak memory 219424 kb
Host smart-70ffdb73-814f-45c7-85eb-616fbef60d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777712998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.777712998 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.2456935837
Short name T399
Test name
Test status
Simulation time 75311551119 ps
CPU time 941.27 seconds
Started Aug 15 05:56:26 PM PDT 24
Finished Aug 15 06:12:08 PM PDT 24
Peak memory 1236244 kb
Host smart-7b450542-b09d-4a94-b7e7-ac974c5df3fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456935837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.2456935837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.1315518200
Short name T608
Test name
Test status
Simulation time 61352618205 ps
CPU time 351.42 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 06:02:17 PM PDT 24
Peak memory 541908 kb
Host smart-b37b731c-3844-43dc-beb1-c18e6afd69b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315518200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1315518200 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2831512704
Short name T330
Test name
Test status
Simulation time 2729485002 ps
CPU time 37 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 05:57:02 PM PDT 24
Peak memory 217920 kb
Host smart-0063e900-e45a-48d1-bd3f-dc4f74ebe3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831512704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2831512704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.2976093345
Short name T507
Test name
Test status
Simulation time 8386960123 ps
CPU time 90.74 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 306060 kb
Host smart-0fc48397-3e9c-4f58-9fe5-ced640ca21d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2976093345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2976093345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_alert_test.3666863535
Short name T204
Test name
Test status
Simulation time 21437214 ps
CPU time 0.82 seconds
Started Aug 15 05:56:32 PM PDT 24
Finished Aug 15 05:56:33 PM PDT 24
Peak memory 204904 kb
Host smart-959a853e-73b2-42da-931a-c55fa20bd0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666863535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3666863535 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3031790791
Short name T350
Test name
Test status
Simulation time 299083545 ps
CPU time 24.02 seconds
Started Aug 15 05:56:26 PM PDT 24
Finished Aug 15 05:56:50 PM PDT 24
Peak memory 226316 kb
Host smart-4d9fdb13-3764-4dc3-8ee1-904fb1c141e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031790791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3031790791 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.2809205892
Short name T280
Test name
Test status
Simulation time 1977630785 ps
CPU time 24.34 seconds
Started Aug 15 05:56:29 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 223696 kb
Host smart-f89cdaf2-55d0-47b3-bbf4-8972e77ddda1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809205892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.280920589
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.855126586
Short name T75
Test name
Test status
Simulation time 122376766496 ps
CPU time 219.6 seconds
Started Aug 15 05:56:22 PM PDT 24
Finished Aug 15 06:00:02 PM PDT 24
Peak memory 412024 kb
Host smart-ac15137e-d5d1-4634-a291-dd73a806c069
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855126586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.85
5126586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3963521349
Short name T498
Test name
Test status
Simulation time 26457877492 ps
CPU time 351.64 seconds
Started Aug 15 05:56:28 PM PDT 24
Finished Aug 15 06:02:20 PM PDT 24
Peak memory 387616 kb
Host smart-d947eaf5-9703-4476-ab8f-8143114e5802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963521349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3963521349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.2215842354
Short name T262
Test name
Test status
Simulation time 2499873626 ps
CPU time 6.74 seconds
Started Aug 15 05:56:23 PM PDT 24
Finished Aug 15 05:56:30 PM PDT 24
Peak memory 217636 kb
Host smart-154d92d8-802a-4fca-ac78-a9ede20ce1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215842354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2215842354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.405531116
Short name T689
Test name
Test status
Simulation time 114094457 ps
CPU time 1.52 seconds
Started Aug 15 05:56:24 PM PDT 24
Finished Aug 15 05:56:26 PM PDT 24
Peak memory 223588 kb
Host smart-2860fcb6-dd83-4087-8e35-8a4fb0ea0807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405531116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.405531116 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.879046296
Short name T553
Test name
Test status
Simulation time 4228388171 ps
CPU time 407.75 seconds
Started Aug 15 05:56:28 PM PDT 24
Finished Aug 15 06:03:16 PM PDT 24
Peak memory 472476 kb
Host smart-1d1e821b-18be-4377-b2e6-fcd6c437b1f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879046296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.879046296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.3657688671
Short name T375
Test name
Test status
Simulation time 1935925464 ps
CPU time 146.59 seconds
Started Aug 15 05:56:25 PM PDT 24
Finished Aug 15 05:58:52 PM PDT 24
Peak memory 285980 kb
Host smart-d3ddcd61-2671-49f8-80a8-1e02d54f20f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657688671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3657688671 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.2067331849
Short name T197
Test name
Test status
Simulation time 7893420529 ps
CPU time 67.8 seconds
Started Aug 15 05:56:20 PM PDT 24
Finished Aug 15 05:57:28 PM PDT 24
Peak memory 222188 kb
Host smart-3503f92b-0728-4efe-8fe0-ce686bafc51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067331849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2067331849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.140375743
Short name T441
Test name
Test status
Simulation time 146924089014 ps
CPU time 165.22 seconds
Started Aug 15 05:56:22 PM PDT 24
Finished Aug 15 05:59:07 PM PDT 24
Peak memory 316140 kb
Host smart-82f9b61d-44f1-423f-8396-dd7fe4d7c1b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=140375743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.140375743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_alert_test.1104968055
Short name T44
Test name
Test status
Simulation time 17040942 ps
CPU time 0.8 seconds
Started Aug 15 05:56:33 PM PDT 24
Finished Aug 15 05:56:34 PM PDT 24
Peak memory 204888 kb
Host smart-1732ea05-33bb-4050-af17-5061af642e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104968055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1104968055 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1763650484
Short name T401
Test name
Test status
Simulation time 34794947912 ps
CPU time 333.49 seconds
Started Aug 15 05:56:31 PM PDT 24
Finished Aug 15 06:02:05 PM PDT 24
Peak memory 352972 kb
Host smart-e9f21c24-6ebc-405c-94e5-c6728ed39b53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763650484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1763650484 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1077026537
Short name T66
Test name
Test status
Simulation time 18816983889 ps
CPU time 681.78 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 248880 kb
Host smart-2a63d6cd-d5cf-4295-9fc6-99e83aab164e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077026537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.107702653
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.3760664825
Short name T590
Test name
Test status
Simulation time 10129819790 ps
CPU time 235.41 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 06:00:26 PM PDT 24
Peak memory 430376 kb
Host smart-303ef080-31e2-419a-ab59-dfdee3dbc3b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760664825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3
760664825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.857143750
Short name T107
Test name
Test status
Simulation time 2190821995 ps
CPU time 44.49 seconds
Started Aug 15 05:56:31 PM PDT 24
Finished Aug 15 05:57:15 PM PDT 24
Peak memory 249096 kb
Host smart-4072ae85-4909-4a3b-9d75-965b4350b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857143750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.857143750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.1434497562
Short name T272
Test name
Test status
Simulation time 124183317 ps
CPU time 1.49 seconds
Started Aug 15 05:56:32 PM PDT 24
Finished Aug 15 05:56:33 PM PDT 24
Peak memory 218444 kb
Host smart-1fafd167-f75c-45e8-be7f-23eb553a2aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434497562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1434497562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.607884769
Short name T657
Test name
Test status
Simulation time 36267927 ps
CPU time 1.38 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 05:56:31 PM PDT 24
Peak memory 216992 kb
Host smart-8845113a-3599-492b-b386-096df406b57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607884769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.607884769 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.353999181
Short name T327
Test name
Test status
Simulation time 61205523044 ps
CPU time 1666.24 seconds
Started Aug 15 05:56:31 PM PDT 24
Finished Aug 15 06:24:17 PM PDT 24
Peak memory 1152064 kb
Host smart-e965cbfe-8572-46eb-a2af-aa25ef479336
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353999181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_an
d_output.353999181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.1986217747
Short name T355
Test name
Test status
Simulation time 32522755528 ps
CPU time 298.81 seconds
Started Aug 15 05:56:32 PM PDT 24
Finished Aug 15 06:01:30 PM PDT 24
Peak memory 348548 kb
Host smart-a5e27b7b-4218-4340-ac73-df985e3e2226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986217747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1986217747 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.317158852
Short name T647
Test name
Test status
Simulation time 2021187000 ps
CPU time 11.56 seconds
Started Aug 15 05:56:31 PM PDT 24
Finished Aug 15 05:56:42 PM PDT 24
Peak memory 217980 kb
Host smart-7190f7d9-6853-45d1-864a-07ffdca1f12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317158852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.317158852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.4267717996
Short name T686
Test name
Test status
Simulation time 10857625727 ps
CPU time 121.85 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 05:58:32 PM PDT 24
Peak memory 256100 kb
Host smart-44dd4ae7-491d-4669-acbe-5346d4006741
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4267717996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.4267717996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_alert_test.4252684527
Short name T362
Test name
Test status
Simulation time 40612283 ps
CPU time 0.74 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 05:56:31 PM PDT 24
Peak memory 204880 kb
Host smart-092f5cbb-a574-48e6-98bd-9cbd4f4b084e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252684527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.4252684527 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1601067637
Short name T410
Test name
Test status
Simulation time 7577525205 ps
CPU time 198.67 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 05:59:49 PM PDT 24
Peak memory 295468 kb
Host smart-8fa43f75-d017-4ab0-8849-5ab46d4cb407
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601067637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1601067637 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.1945638195
Short name T681
Test name
Test status
Simulation time 9148576866 ps
CPU time 353.54 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 06:02:24 PM PDT 24
Peak memory 240228 kb
Host smart-8ec0eb66-5076-4247-b632-937918aa3e48
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945638195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.194563819
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2860542405
Short name T653
Test name
Test status
Simulation time 4388264484 ps
CPU time 122.87 seconds
Started Aug 15 05:56:32 PM PDT 24
Finished Aug 15 05:58:35 PM PDT 24
Peak memory 265172 kb
Host smart-ba8a8ba5-2824-4a62-a023-c6e3a46b49e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860542405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2
860542405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3408518255
Short name T451
Test name
Test status
Simulation time 4223618692 ps
CPU time 302.18 seconds
Started Aug 15 05:56:35 PM PDT 24
Finished Aug 15 06:01:37 PM PDT 24
Peak memory 364300 kb
Host smart-6382b69e-b473-4e78-8dda-c071c047fda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408518255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3408518255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.3333605562
Short name T300
Test name
Test status
Simulation time 2391781345 ps
CPU time 6.42 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 05:56:37 PM PDT 24
Peak memory 217692 kb
Host smart-71c28a51-37f2-4aa4-a81b-58d36cb6e92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333605562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3333605562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.2800485560
Short name T185
Test name
Test status
Simulation time 14364343752 ps
CPU time 674.57 seconds
Started Aug 15 05:56:30 PM PDT 24
Finished Aug 15 06:07:45 PM PDT 24
Peak memory 635908 kb
Host smart-c6726c40-77fe-4a1d-b810-1058707ec224
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800485560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.2800485560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.1390503058
Short name T627
Test name
Test status
Simulation time 34881457670 ps
CPU time 180.71 seconds
Started Aug 15 05:56:29 PM PDT 24
Finished Aug 15 05:59:30 PM PDT 24
Peak memory 391552 kb
Host smart-ceef25a6-a066-4491-a386-5775ff2a9753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390503058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1390503058 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.606826005
Short name T202
Test name
Test status
Simulation time 850178846 ps
CPU time 41.49 seconds
Started Aug 15 05:56:33 PM PDT 24
Finished Aug 15 05:57:15 PM PDT 24
Peak memory 222408 kb
Host smart-8812d313-16f1-45fd-af40-b502435be507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606826005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.606826005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.618568533
Short name T586
Test name
Test status
Simulation time 1038345483 ps
CPU time 2.5 seconds
Started Aug 15 05:56:31 PM PDT 24
Finished Aug 15 05:56:33 PM PDT 24
Peak memory 221224 kb
Host smart-228bf875-4691-4eb2-a323-ff3687054d45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=618568533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.618568533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_alert_test.1357779566
Short name T696
Test name
Test status
Simulation time 18710428 ps
CPU time 0.81 seconds
Started Aug 15 05:55:34 PM PDT 24
Finished Aug 15 05:55:35 PM PDT 24
Peak memory 204936 kb
Host smart-82c50bd2-fbc0-415d-b294-d3712cea9e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357779566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1357779566 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.1663656316
Short name T416
Test name
Test status
Simulation time 57949946199 ps
CPU time 160.97 seconds
Started Aug 15 05:56:12 PM PDT 24
Finished Aug 15 05:58:53 PM PDT 24
Peak memory 348736 kb
Host smart-c2bae46f-2bc0-4d1c-aca7-f556c418b2b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663656316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.1663656316 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.204644256
Short name T233
Test name
Test status
Simulation time 3208707430 ps
CPU time 63.85 seconds
Started Aug 15 05:55:41 PM PDT 24
Finished Aug 15 05:56:45 PM PDT 24
Peak memory 244384 kb
Host smart-d52ace96-b6dd-47da-9d8b-913fd183443d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204644256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_part
ial_data.204644256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.906754026
Short name T178
Test name
Test status
Simulation time 27502403582 ps
CPU time 628.89 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 238748 kb
Host smart-15fa3172-45b3-490e-8823-5eebd9ce7429
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906754026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.906754026 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.93899136
Short name T629
Test name
Test status
Simulation time 1438041189 ps
CPU time 12.02 seconds
Started Aug 15 05:55:54 PM PDT 24
Finished Aug 15 05:56:12 PM PDT 24
Peak memory 215392 kb
Host smart-3b1689d1-8c37-42fc-b1ed-e672d37e0725
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93899136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.93899136 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1787301037
Short name T582
Test name
Test status
Simulation time 965064101 ps
CPU time 35.51 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:56:08 PM PDT 24
Peak memory 223584 kb
Host smart-f44eb9ce-6f8e-44e9-a28f-5c8367d928ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1787301037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1787301037 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.3060378627
Short name T522
Test name
Test status
Simulation time 5996830409 ps
CPU time 50.9 seconds
Started Aug 15 05:55:39 PM PDT 24
Finished Aug 15 05:56:30 PM PDT 24
Peak memory 218216 kb
Host smart-e828d9fa-e485-4f48-a14b-2eec3afe4a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060378627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3060378627 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.1226968955
Short name T725
Test name
Test status
Simulation time 60610171216 ps
CPU time 287.03 seconds
Started Aug 15 05:55:40 PM PDT 24
Finished Aug 15 06:00:27 PM PDT 24
Peak memory 471668 kb
Host smart-4394e0f9-6d79-4376-8cd3-947805c6a981
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226968955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.12
26968955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.3817440607
Short name T31
Test name
Test status
Simulation time 6943904811 ps
CPU time 276.01 seconds
Started Aug 15 05:55:44 PM PDT 24
Finished Aug 15 06:00:21 PM PDT 24
Peak memory 344624 kb
Host smart-14f4661b-553d-49a3-aa28-c62d55928468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817440607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3817440607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.1614152785
Short name T20
Test name
Test status
Simulation time 473096543 ps
CPU time 3.25 seconds
Started Aug 15 05:55:49 PM PDT 24
Finished Aug 15 05:55:53 PM PDT 24
Peak memory 217296 kb
Host smart-dc777797-0d38-44fa-a280-00e7b2fdc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614152785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1614152785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.677264975
Short name T602
Test name
Test status
Simulation time 156337435 ps
CPU time 1.62 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:55:33 PM PDT 24
Peak memory 217060 kb
Host smart-7e81350e-7aaf-45e4-874f-424791dbd39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677264975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.677264975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2461012941
Short name T449
Test name
Test status
Simulation time 10113648070 ps
CPU time 930.95 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 06:11:03 PM PDT 24
Peak memory 799416 kb
Host smart-11948cc7-552f-49c5-92f3-b79980e54fc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461012941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2461012941 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1834103103
Short name T11
Test name
Test status
Simulation time 2912943029 ps
CPU time 22.13 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:55:55 PM PDT 24
Peak memory 245316 kb
Host smart-68272556-b173-4ef5-8907-772c386081f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834103103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1834103103 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.550018621
Short name T497
Test name
Test status
Simulation time 23372913960 ps
CPU time 479.1 seconds
Started Aug 15 05:55:34 PM PDT 24
Finished Aug 15 06:03:33 PM PDT 24
Peak memory 644564 kb
Host smart-fce2ec83-f3c6-4585-8b0a-36e67d492568
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550018621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.550018621 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.4137888151
Short name T466
Test name
Test status
Simulation time 9522429859 ps
CPU time 57.96 seconds
Started Aug 15 05:55:28 PM PDT 24
Finished Aug 15 05:56:26 PM PDT 24
Peak memory 223908 kb
Host smart-5886d9df-2b87-4aa3-8462-8e3386afc7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137888151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4137888151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.4050484724
Short name T288
Test name
Test status
Simulation time 431345252922 ps
CPU time 1668.07 seconds
Started Aug 15 05:55:41 PM PDT 24
Finished Aug 15 06:23:29 PM PDT 24
Peak memory 885972 kb
Host smart-de923357-8f93-4f71-9a45-1bf28b23aadf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4050484724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.4050484724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3642553688
Short name T199
Test name
Test status
Simulation time 292808004 ps
CPU time 2.11 seconds
Started Aug 15 05:56:12 PM PDT 24
Finished Aug 15 05:56:14 PM PDT 24
Peak memory 217768 kb
Host smart-08ab2f45-65a3-4e80-80fe-963f3c7048bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642553688 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3642553688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3428453725
Short name T348
Test name
Test status
Simulation time 86353798 ps
CPU time 2.15 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 05:56:12 PM PDT 24
Peak memory 217412 kb
Host smart-d18f1fda-af63-418c-b269-17deb426e442
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428453725 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3428453725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.3522550988
Short name T556
Test name
Test status
Simulation time 77234922849 ps
CPU time 2876.69 seconds
Started Aug 15 05:55:29 PM PDT 24
Finished Aug 15 06:43:26 PM PDT 24
Peak memory 2937064 kb
Host smart-a7be2338-cd22-495f-b5f5-7e8d4ba3637a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3522550988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3522550988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3586440659
Short name T651
Test name
Test status
Simulation time 62452712916 ps
CPU time 1377.05 seconds
Started Aug 15 05:55:37 PM PDT 24
Finished Aug 15 06:18:34 PM PDT 24
Peak memory 924336 kb
Host smart-778896d1-702a-4fcc-8093-fcbbbf122987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3586440659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3586440659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.633885746
Short name T260
Test name
Test status
Simulation time 97221132726 ps
CPU time 1414.07 seconds
Started Aug 15 05:55:51 PM PDT 24
Finished Aug 15 06:19:26 PM PDT 24
Peak memory 1730912 kb
Host smart-9c87f405-854a-449e-9e56-8c1d2f39dfc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=633885746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.633885746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.3300744028
Short name T675
Test name
Test status
Simulation time 20362513490 ps
CPU time 2086.56 seconds
Started Aug 15 05:55:42 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 1320808 kb
Host smart-d39e0af4-e700-44cc-9370-8e7d3b5080fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3300744028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3300744028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.103600536
Short name T187
Test name
Test status
Simulation time 56816837387 ps
CPU time 2453.11 seconds
Started Aug 15 05:55:49 PM PDT 24
Finished Aug 15 06:36:42 PM PDT 24
Peak memory 2929404 kb
Host smart-09f4c897-b8f4-4a5b-ad21-20fe1145431b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=103600536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.103600536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2892422094
Short name T587
Test name
Test status
Simulation time 45617302 ps
CPU time 0.79 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 05:56:40 PM PDT 24
Peak memory 204904 kb
Host smart-f085243c-2de6-4a38-9032-9444a6bb61e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892422094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2892422094 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.3937498545
Short name T353
Test name
Test status
Simulation time 8395160047 ps
CPU time 215.21 seconds
Started Aug 15 05:56:41 PM PDT 24
Finished Aug 15 06:00:16 PM PDT 24
Peak memory 425368 kb
Host smart-9d932e41-f0e1-4559-822f-6111ed6dfff8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937498545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3937498545 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.1500074108
Short name T142
Test name
Test status
Simulation time 4774712824 ps
CPU time 154.85 seconds
Started Aug 15 05:56:40 PM PDT 24
Finished Aug 15 05:59:15 PM PDT 24
Peak memory 226600 kb
Host smart-3fbd8ccd-f24e-4d32-8a9f-6e8fe41d6c0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500074108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.150007410
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.3758773777
Short name T518
Test name
Test status
Simulation time 27115729002 ps
CPU time 344.77 seconds
Started Aug 15 05:56:52 PM PDT 24
Finished Aug 15 06:02:37 PM PDT 24
Peak memory 504120 kb
Host smart-cf22dc27-711a-4553-ad21-ca676adc2ce0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758773777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3
758773777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.2799755190
Short name T287
Test name
Test status
Simulation time 9845498608 ps
CPU time 275.68 seconds
Started Aug 15 05:56:41 PM PDT 24
Finished Aug 15 06:01:17 PM PDT 24
Peak memory 473344 kb
Host smart-88549c59-4ae2-41b1-be3e-447548f4aed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799755190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2799755190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2240546794
Short name T438
Test name
Test status
Simulation time 86244207 ps
CPU time 1.04 seconds
Started Aug 15 05:56:49 PM PDT 24
Finished Aug 15 05:56:50 PM PDT 24
Peak memory 217096 kb
Host smart-41b9479b-66cf-44ee-96f8-19f122fb6aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240546794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2240546794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.4084448039
Short name T4
Test name
Test status
Simulation time 118112152 ps
CPU time 1.31 seconds
Started Aug 15 05:56:49 PM PDT 24
Finished Aug 15 05:56:50 PM PDT 24
Peak memory 217424 kb
Host smart-92100d7f-ac3a-4299-a288-dd07e7d565da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084448039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.4084448039 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_sideload.3279412443
Short name T652
Test name
Test status
Simulation time 12949354635 ps
CPU time 68.53 seconds
Started Aug 15 05:56:36 PM PDT 24
Finished Aug 15 05:57:44 PM PDT 24
Peak memory 278748 kb
Host smart-e80ee11e-e9c4-4478-a5f5-23e0919476d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279412443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3279412443 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2176241974
Short name T465
Test name
Test status
Simulation time 5220502776 ps
CPU time 29 seconds
Started Aug 15 05:56:40 PM PDT 24
Finished Aug 15 05:57:09 PM PDT 24
Peak memory 218008 kb
Host smart-db552f12-ccf6-4ed7-8227-bbcdeb767f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176241974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2176241974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1671539543
Short name T684
Test name
Test status
Simulation time 221915263965 ps
CPU time 1465.39 seconds
Started Aug 15 05:56:50 PM PDT 24
Finished Aug 15 06:21:16 PM PDT 24
Peak memory 1400740 kb
Host smart-1ab9ab84-dccf-42c7-8846-340ff02ca8fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1671539543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1671539543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1745579924
Short name T192
Test name
Test status
Simulation time 47030596 ps
CPU time 0.81 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 05:56:40 PM PDT 24
Peak memory 204856 kb
Host smart-d3663584-06c9-4822-b404-b43cc8e869aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745579924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1745579924 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3955170976
Short name T519
Test name
Test status
Simulation time 10478170317 ps
CPU time 287.89 seconds
Started Aug 15 05:56:49 PM PDT 24
Finished Aug 15 06:01:37 PM PDT 24
Peak memory 335740 kb
Host smart-a122aa7f-db02-4c3b-9048-13645e2b989d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955170976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3955170976 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.975336477
Short name T284
Test name
Test status
Simulation time 1562791071 ps
CPU time 12.43 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 05:56:51 PM PDT 24
Peak memory 219344 kb
Host smart-66ce16a5-afb2-4228-83e1-d74059852729
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975336477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.975336477
+enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.307997336
Short name T695
Test name
Test status
Simulation time 5723667011 ps
CPU time 228.11 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 06:00:27 PM PDT 24
Peak memory 308848 kb
Host smart-ef5225e5-797b-4258-903b-e8f12e91abc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307997336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.30
7997336 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.3327891060
Short name T448
Test name
Test status
Simulation time 34838422604 ps
CPU time 433.36 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 06:04:02 PM PDT 24
Peak memory 582652 kb
Host smart-76bda144-8f26-4f27-ab26-2bcbc5257cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327891060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3327891060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1782147896
Short name T59
Test name
Test status
Simulation time 3368555249 ps
CPU time 9.5 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 05:56:58 PM PDT 24
Peak memory 218852 kb
Host smart-7317b6fc-34e0-46c4-b84e-aafafafe8714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782147896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1782147896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.2796396780
Short name T57
Test name
Test status
Simulation time 59303858 ps
CPU time 1.42 seconds
Started Aug 15 05:56:52 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 218656 kb
Host smart-374399c7-2b02-4f4d-a4c7-1becb7d26347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796396780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2796396780 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.208891321
Short name T673
Test name
Test status
Simulation time 26691367197 ps
CPU time 3276.56 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 06:51:16 PM PDT 24
Peak memory 1854548 kb
Host smart-4bb55637-e382-468e-8105-858023cd957f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208891321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_an
d_output.208891321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.3190181019
Short name T368
Test name
Test status
Simulation time 21863042650 ps
CPU time 301.63 seconds
Started Aug 15 05:56:49 PM PDT 24
Finished Aug 15 06:01:51 PM PDT 24
Peak memory 519540 kb
Host smart-ad4d47c9-066a-4c51-87cb-14ce527ddaf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190181019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3190181019 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.1468948798
Short name T430
Test name
Test status
Simulation time 1313206514 ps
CPU time 16.71 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 05:56:55 PM PDT 24
Peak memory 220464 kb
Host smart-4ff28669-88e7-48a9-87a8-1a23707f141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468948798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1468948798 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.203045751
Short name T103
Test name
Test status
Simulation time 5118855924 ps
CPU time 85.74 seconds
Started Aug 15 05:56:37 PM PDT 24
Finished Aug 15 05:58:03 PM PDT 24
Peak memory 276196 kb
Host smart-25327a2d-eb4f-45f3-b260-d9eb40a84b0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=203045751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.203045751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_alert_test.1004080350
Short name T45
Test name
Test status
Simulation time 16693851 ps
CPU time 0.77 seconds
Started Aug 15 05:56:47 PM PDT 24
Finished Aug 15 05:56:48 PM PDT 24
Peak memory 204936 kb
Host smart-0f8a957d-a871-4a3c-a349-454bd0623af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004080350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1004080350 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.1996878058
Short name T159
Test name
Test status
Simulation time 4172229676 ps
CPU time 49.31 seconds
Started Aug 15 05:56:52 PM PDT 24
Finished Aug 15 05:57:41 PM PDT 24
Peak memory 239344 kb
Host smart-e6f0f624-f998-4d40-a307-36cbf0933b2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996878058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1996878058 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.522690881
Short name T392
Test name
Test status
Simulation time 12983361734 ps
CPU time 521.94 seconds
Started Aug 15 05:56:38 PM PDT 24
Finished Aug 15 06:05:20 PM PDT 24
Peak memory 243928 kb
Host smart-12434ec5-f327-453b-9b43-40c9013d42f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522690881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.522690881
+enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2631300303
Short name T450
Test name
Test status
Simulation time 220810117888 ps
CPU time 212.68 seconds
Started Aug 15 05:56:41 PM PDT 24
Finished Aug 15 06:00:14 PM PDT 24
Peak memory 414564 kb
Host smart-70fa854d-9ec2-4ae8-b056-9f04ae34b757
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631300303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2
631300303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3083126126
Short name T636
Test name
Test status
Simulation time 11126816047 ps
CPU time 129.31 seconds
Started Aug 15 05:56:56 PM PDT 24
Finished Aug 15 05:59:05 PM PDT 24
Peak memory 338432 kb
Host smart-64b987ee-3502-4b1a-9af7-a9033b03bc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083126126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3083126126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.4184879080
Short name T256
Test name
Test status
Simulation time 399792782 ps
CPU time 2.85 seconds
Started Aug 15 05:56:50 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 217608 kb
Host smart-59f1ff33-4ff4-4240-a7ea-10cceda72c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184879080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.4184879080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.1925397574
Short name T452
Test name
Test status
Simulation time 131632803 ps
CPU time 1.22 seconds
Started Aug 15 05:56:38 PM PDT 24
Finished Aug 15 05:56:40 PM PDT 24
Peak memory 218844 kb
Host smart-1d207b13-80a9-48e4-ac4d-d45f17445065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925397574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1925397574 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_sideload.868780640
Short name T727
Test name
Test status
Simulation time 16666466838 ps
CPU time 122.22 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 05:58:41 PM PDT 24
Peak memory 319452 kb
Host smart-8306dd3f-9983-462f-8c72-3d5b8b0c8048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868780640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.868780640 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.2072938487
Short name T542
Test name
Test status
Simulation time 1677895071 ps
CPU time 37.29 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 05:57:16 PM PDT 24
Peak memory 217952 kb
Host smart-cf7b1e31-d1d6-439c-ba9a-e3c4942864fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072938487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2072938487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.4201554718
Short name T532
Test name
Test status
Simulation time 30251529411 ps
CPU time 1754.2 seconds
Started Aug 15 05:56:38 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 749740 kb
Host smart-00ab27e5-e91a-4d06-991d-661914c8fb98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4201554718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.4201554718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_alert_test.1281027677
Short name T406
Test name
Test status
Simulation time 59012479 ps
CPU time 0.84 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 05:56:49 PM PDT 24
Peak memory 204940 kb
Host smart-fb25c7af-1732-43d6-b840-17caf8b690fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281027677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.1281027677 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.3132043367
Short name T717
Test name
Test status
Simulation time 9549269569 ps
CPU time 144.83 seconds
Started Aug 15 05:56:40 PM PDT 24
Finished Aug 15 05:59:05 PM PDT 24
Peak memory 276496 kb
Host smart-915fd0d5-2c01-4539-88b5-44bebf1446a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132043367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3132043367 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.1276207097
Short name T511
Test name
Test status
Simulation time 33679300761 ps
CPU time 787.74 seconds
Started Aug 15 05:56:49 PM PDT 24
Finished Aug 15 06:09:57 PM PDT 24
Peak memory 241036 kb
Host smart-5bda3a04-a93a-489d-9d22-9fb2f1cdf6e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276207097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.127620709
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.324348366
Short name T688
Test name
Test status
Simulation time 17526715071 ps
CPU time 195.23 seconds
Started Aug 15 05:56:50 PM PDT 24
Finished Aug 15 06:00:05 PM PDT 24
Peak memory 299860 kb
Host smart-b2f78e3c-71b9-405f-8aaa-9ff5879ba274
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324348366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.32
4348366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.1026972377
Short name T680
Test name
Test status
Simulation time 17680414663 ps
CPU time 275.73 seconds
Started Aug 15 05:56:39 PM PDT 24
Finished Aug 15 06:01:15 PM PDT 24
Peak memory 467564 kb
Host smart-ce1aef4d-c911-47c7-9fe3-ad38c12b644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026972377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1026972377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.202179900
Short name T63
Test name
Test status
Simulation time 3585420865 ps
CPU time 5.2 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 217748 kb
Host smart-87803b4e-6939-44e0-be99-5e92e770a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202179900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.202179900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1848144694
Short name T568
Test name
Test status
Simulation time 194451180 ps
CPU time 1.3 seconds
Started Aug 15 05:56:49 PM PDT 24
Finished Aug 15 05:56:50 PM PDT 24
Peak memory 218988 kb
Host smart-f47e7502-0e82-4eee-9b7f-99e0629ae208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848144694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1848144694 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1334080609
Short name T559
Test name
Test status
Simulation time 25514471983 ps
CPU time 2852.03 seconds
Started Aug 15 05:56:38 PM PDT 24
Finished Aug 15 06:44:11 PM PDT 24
Peak memory 1703028 kb
Host smart-f227bbea-2081-4d0d-a18d-d5be599b97df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334080609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1334080609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.4275046528
Short name T365
Test name
Test status
Simulation time 3338006070 ps
CPU time 235.38 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 328856 kb
Host smart-5ca75801-5970-4373-8d6b-83bfcebd7f6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275046528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.4275046528 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.2330667
Short name T529
Test name
Test status
Simulation time 2778589146 ps
CPU time 57.05 seconds
Started Aug 15 05:56:51 PM PDT 24
Finished Aug 15 05:57:48 PM PDT 24
Peak memory 221292 kb
Host smart-b050da58-80dd-430a-a88f-02317c8f40bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2330667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.778868600
Short name T376
Test name
Test status
Simulation time 10142378059 ps
CPU time 242.4 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 06:00:51 PM PDT 24
Peak memory 329308 kb
Host smart-aa5cee22-e0d0-41b0-ba68-9a388a09586b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=778868600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.778868600 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_alert_test.105899408
Short name T229
Test name
Test status
Simulation time 320016299 ps
CPU time 0.92 seconds
Started Aug 15 05:56:47 PM PDT 24
Finished Aug 15 05:56:48 PM PDT 24
Peak memory 204940 kb
Host smart-27188ddd-987a-4b3c-bf24-9811b4db034c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105899408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.105899408 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.1953846007
Short name T564
Test name
Test status
Simulation time 76770616 ps
CPU time 5.36 seconds
Started Aug 15 05:57:01 PM PDT 24
Finished Aug 15 05:57:07 PM PDT 24
Peak memory 222816 kb
Host smart-ea51842c-5c2f-4eea-9da6-489470708e81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953846007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1953846007 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.168903174
Short name T363
Test name
Test status
Simulation time 47358440919 ps
CPU time 396.75 seconds
Started Aug 15 05:56:58 PM PDT 24
Finished Aug 15 06:03:35 PM PDT 24
Peak memory 233632 kb
Host smart-44a96fed-fb89-4caf-a17c-d924f71a9152
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168903174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.168903174
+enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_error.878547686
Short name T578
Test name
Test status
Simulation time 5448516459 ps
CPU time 40.82 seconds
Started Aug 15 05:56:47 PM PDT 24
Finished Aug 15 05:57:28 PM PDT 24
Peak memory 255356 kb
Host smart-bbb7d1cd-4a49-4c09-968d-9946d196c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878547686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.878547686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.2880732196
Short name T225
Test name
Test status
Simulation time 908984372 ps
CPU time 4.45 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 05:57:07 PM PDT 24
Peak memory 217316 kb
Host smart-703b8972-a6d8-4c55-a977-79d3fea7693f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880732196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2880732196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2588626116
Short name T33
Test name
Test status
Simulation time 55998109 ps
CPU time 1.36 seconds
Started Aug 15 05:56:58 PM PDT 24
Finished Aug 15 05:57:00 PM PDT 24
Peak memory 218472 kb
Host smart-7e90958b-1773-42d6-b69f-b908a29a712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588626116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2588626116 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.1672081173
Short name T445
Test name
Test status
Simulation time 19482859837 ps
CPU time 765.62 seconds
Started Aug 15 05:57:00 PM PDT 24
Finished Aug 15 06:09:46 PM PDT 24
Peak memory 1090804 kb
Host smart-347f6a6c-dd42-48c2-ab85-68b9b5328e5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672081173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.1672081173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.310898741
Short name T304
Test name
Test status
Simulation time 852375443 ps
CPU time 23.53 seconds
Started Aug 15 05:56:57 PM PDT 24
Finished Aug 15 05:57:21 PM PDT 24
Peak memory 226260 kb
Host smart-e21bb97d-0eb1-42b6-9412-73764e2f2d61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310898741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.310898741 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.334841088
Short name T546
Test name
Test status
Simulation time 3052537499 ps
CPU time 49.38 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 05:57:51 PM PDT 24
Peak memory 218972 kb
Host smart-50c38451-f189-4a16-9e0c-fcf7c0e08a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334841088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.334841088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.2399933667
Short name T513
Test name
Test status
Simulation time 38031785696 ps
CPU time 1332.11 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 06:19:01 PM PDT 24
Peak memory 1140296 kb
Host smart-2f657b24-b7a8-412c-9572-df405ba39ca2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2399933667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2399933667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_alert_test.2188263036
Short name T504
Test name
Test status
Simulation time 37034012 ps
CPU time 0.82 seconds
Started Aug 15 05:57:06 PM PDT 24
Finished Aug 15 05:57:07 PM PDT 24
Peak memory 204904 kb
Host smart-0cd0d76f-c61b-4e9e-a118-861301a9485a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188263036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2188263036 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.3676875879
Short name T389
Test name
Test status
Simulation time 4031569354 ps
CPU time 29.05 seconds
Started Aug 15 05:56:59 PM PDT 24
Finished Aug 15 05:57:28 PM PDT 24
Peak memory 242032 kb
Host smart-fc42b50f-9f39-4b97-8767-ed006d81b0d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676875879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3676875879 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.1846675030
Short name T418
Test name
Test status
Simulation time 61247365263 ps
CPU time 992.18 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 06:13:20 PM PDT 24
Peak memory 258908 kb
Host smart-725e0385-0c6d-4fae-a96d-8223e67d73b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846675030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.184667503
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3373441816
Short name T437
Test name
Test status
Simulation time 6204571177 ps
CPU time 56.56 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 05:57:45 PM PDT 24
Peak memory 267068 kb
Host smart-115115ae-5766-4e09-bb68-d1c72d08f34e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373441816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3
373441816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.525933679
Short name T545
Test name
Test status
Simulation time 5964915335 ps
CPU time 217.95 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 06:00:33 PM PDT 24
Peak memory 324856 kb
Host smart-4645a7c7-a483-4e32-993a-abf18d0280d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525933679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.525933679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.1655826823
Short name T366
Test name
Test status
Simulation time 2300133372 ps
CPU time 5.71 seconds
Started Aug 15 05:56:56 PM PDT 24
Finished Aug 15 05:57:02 PM PDT 24
Peak memory 217680 kb
Host smart-8f37a152-c72e-401f-8df1-1657a6aec233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655826823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1655826823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.3744851087
Short name T205
Test name
Test status
Simulation time 67117314264 ps
CPU time 1051.48 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 06:14:20 PM PDT 24
Peak memory 1465264 kb
Host smart-c9fe4c39-3a7a-473c-8997-bbda4600a9f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744851087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.3744851087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.897911808
Short name T210
Test name
Test status
Simulation time 423970815 ps
CPU time 32.17 seconds
Started Aug 15 05:56:46 PM PDT 24
Finished Aug 15 05:57:18 PM PDT 24
Peak memory 229864 kb
Host smart-9fc43d72-322a-4f43-a575-17b19bb69dad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897911808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.897911808 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.4247537655
Short name T379
Test name
Test status
Simulation time 7734856567 ps
CPU time 65.79 seconds
Started Aug 15 05:56:57 PM PDT 24
Finished Aug 15 05:58:03 PM PDT 24
Peak memory 222204 kb
Host smart-cf09179e-61cb-4e55-8a97-1313fd3fb433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247537655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.4247537655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.1571756307
Short name T23
Test name
Test status
Simulation time 25822294116 ps
CPU time 473.42 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 06:04:49 PM PDT 24
Peak memory 354908 kb
Host smart-6447e50d-0bbf-4f70-96c7-5d26e23475d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1571756307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1571756307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_alert_test.4070390467
Short name T543
Test name
Test status
Simulation time 14472286 ps
CPU time 0.81 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 05:56:56 PM PDT 24
Peak memory 204868 kb
Host smart-e41b7e8e-4a84-446b-960c-9fb862564944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070390467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.4070390467 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.3351169598
Short name T617
Test name
Test status
Simulation time 39302367848 ps
CPU time 137.22 seconds
Started Aug 15 05:56:46 PM PDT 24
Finished Aug 15 05:59:03 PM PDT 24
Peak memory 320228 kb
Host smart-fdb33e55-84e1-43fc-ad99-9ddce1f0efc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351169598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3351169598 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.582237363
Short name T344
Test name
Test status
Simulation time 1194242550 ps
CPU time 38.74 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 05:57:27 PM PDT 24
Peak memory 222288 kb
Host smart-d37bfecf-afd4-4824-9929-53a492a1dd93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582237363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.582237363
+enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.1224775478
Short name T373
Test name
Test status
Simulation time 24808533021 ps
CPU time 233.48 seconds
Started Aug 15 05:56:53 PM PDT 24
Finished Aug 15 06:00:46 PM PDT 24
Peak memory 319324 kb
Host smart-4dac2818-f9bb-4baf-83fb-109887696d14
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224775478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1
224775478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.479137132
Short name T650
Test name
Test status
Simulation time 20557017311 ps
CPU time 313.18 seconds
Started Aug 15 05:56:47 PM PDT 24
Finished Aug 15 06:02:01 PM PDT 24
Peak memory 506972 kb
Host smart-4ffa16cd-13b1-456e-a100-02fbc072e521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479137132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.479137132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.4097480744
Short name T596
Test name
Test status
Simulation time 721843333 ps
CPU time 3.22 seconds
Started Aug 15 05:56:47 PM PDT 24
Finished Aug 15 05:56:51 PM PDT 24
Peak memory 217368 kb
Host smart-70acc2a6-c7aa-4515-8a11-20a323c8787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097480744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.4097480744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.569010839
Short name T704
Test name
Test status
Simulation time 41072272 ps
CPU time 1.41 seconds
Started Aug 15 05:56:48 PM PDT 24
Finished Aug 15 05:56:50 PM PDT 24
Peak memory 217072 kb
Host smart-8a92a189-7138-49ba-a9cf-ef9a4d6cfeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569010839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.569010839 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.3177653155
Short name T193
Test name
Test status
Simulation time 46492210058 ps
CPU time 2711.24 seconds
Started Aug 15 05:57:00 PM PDT 24
Finished Aug 15 06:42:11 PM PDT 24
Peak memory 1702808 kb
Host smart-110c74e5-b2bf-43bf-b2d0-9a82b59d7b3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177653155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.3177653155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.2093300556
Short name T337
Test name
Test status
Simulation time 33889205085 ps
CPU time 196 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 06:00:11 PM PDT 24
Peak memory 407908 kb
Host smart-46dafda6-b869-47ac-bb92-8dbc35337ae0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093300556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2093300556 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.3604860989
Short name T527
Test name
Test status
Simulation time 15385144021 ps
CPU time 28.19 seconds
Started Aug 15 05:56:45 PM PDT 24
Finished Aug 15 05:57:14 PM PDT 24
Peak memory 223840 kb
Host smart-37e95e63-1c57-403e-954e-572b172840b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604860989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3604860989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.3617536135
Short name T396
Test name
Test status
Simulation time 27586300177 ps
CPU time 595.89 seconds
Started Aug 15 05:56:50 PM PDT 24
Finished Aug 15 06:06:46 PM PDT 24
Peak memory 463380 kb
Host smart-12f02a74-2f02-4f0a-bb0c-74efedccc94f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3617536135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3617536135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_alert_test.3895754333
Short name T200
Test name
Test status
Simulation time 53440149 ps
CPU time 0.81 seconds
Started Aug 15 05:57:07 PM PDT 24
Finished Aug 15 05:57:08 PM PDT 24
Peak memory 204912 kb
Host smart-52d37829-83c3-4dac-a539-00a6bdb3ba75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895754333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3895754333 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.2803005039
Short name T212
Test name
Test status
Simulation time 49548273561 ps
CPU time 355.36 seconds
Started Aug 15 05:56:54 PM PDT 24
Finished Aug 15 06:02:49 PM PDT 24
Peak memory 530604 kb
Host smart-789f1fa5-4354-4c81-a68d-73582da09f27
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803005039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2803005039 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.3468390914
Short name T38
Test name
Test status
Simulation time 5943193241 ps
CPU time 253.15 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 06:01:16 PM PDT 24
Peak memory 228672 kb
Host smart-f86da4d2-ba6c-42e4-8788-e958873cf4eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468390914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.346839091
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.960271998
Short name T604
Test name
Test status
Simulation time 13771975229 ps
CPU time 176.15 seconds
Started Aug 15 05:56:52 PM PDT 24
Finished Aug 15 05:59:49 PM PDT 24
Peak memory 289008 kb
Host smart-2b73fc25-8089-4dff-b534-b309a5ce8b46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960271998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.96
0271998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.1014465805
Short name T431
Test name
Test status
Simulation time 1056978050 ps
CPU time 43.2 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 05:57:38 PM PDT 24
Peak memory 248344 kb
Host smart-6fd443a3-367e-4543-a962-163784e2527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014465805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1014465805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.1608117485
Short name T719
Test name
Test status
Simulation time 5688965242 ps
CPU time 7.07 seconds
Started Aug 15 05:56:52 PM PDT 24
Finished Aug 15 05:56:59 PM PDT 24
Peak memory 217744 kb
Host smart-1e87200e-e8a2-496e-abc8-59d54ad51ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608117485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1608117485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.3039966700
Short name T571
Test name
Test status
Simulation time 77806083 ps
CPU time 1.55 seconds
Started Aug 15 05:56:56 PM PDT 24
Finished Aug 15 05:56:58 PM PDT 24
Peak memory 223504 kb
Host smart-45221c91-21f7-46ee-85e5-f6afa2f9c2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039966700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3039966700 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.888477436
Short name T435
Test name
Test status
Simulation time 56304394139 ps
CPU time 1489.64 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 06:22:03 PM PDT 24
Peak memory 1073472 kb
Host smart-74a3e66c-b40b-4a83-bd86-1b1b858ce98d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888477436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an
d_output.888477436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.3632874823
Short name T413
Test name
Test status
Simulation time 9472471475 ps
CPU time 142.76 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 05:59:18 PM PDT 24
Peak memory 351648 kb
Host smart-b2128057-4522-43d8-838c-7589ff4542d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632874823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3632874823 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.4204432194
Short name T234
Test name
Test status
Simulation time 4628984053 ps
CPU time 48.57 seconds
Started Aug 15 05:56:56 PM PDT 24
Finished Aug 15 05:57:45 PM PDT 24
Peak memory 219732 kb
Host smart-c148e2e7-67f6-48a5-b4bc-d9a9861fddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204432194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.4204432194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.491695705
Short name T701
Test name
Test status
Simulation time 21825925087 ps
CPU time 424.9 seconds
Started Aug 15 05:56:56 PM PDT 24
Finished Aug 15 06:04:01 PM PDT 24
Peak memory 444840 kb
Host smart-ff7b6779-ff9c-4c72-8c15-cfab8fb36731
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=491695705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.491695705 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_alert_test.1012532231
Short name T329
Test name
Test status
Simulation time 13571562 ps
CPU time 0.78 seconds
Started Aug 15 05:56:52 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 204964 kb
Host smart-db6b0397-d091-49d2-aeee-169e84bca19a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012532231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1012532231 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1386345115
Short name T550
Test name
Test status
Simulation time 12009203552 ps
CPU time 283.16 seconds
Started Aug 15 05:56:58 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 478772 kb
Host smart-71192782-9727-4051-8dc0-587b0b3575da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386345115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1386345115 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.2023822336
Short name T191
Test name
Test status
Simulation time 24352230059 ps
CPU time 799.41 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 06:10:14 PM PDT 24
Peak memory 250808 kb
Host smart-0a9547ce-7af3-4e8f-9c69-1387d190488a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023822336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.202382233
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.1089993271
Short name T549
Test name
Test status
Simulation time 17008132141 ps
CPU time 136.9 seconds
Started Aug 15 05:57:11 PM PDT 24
Finished Aug 15 05:59:28 PM PDT 24
Peak memory 274888 kb
Host smart-4a453dbd-efd2-4b16-a66d-895eb2faf2b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089993271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1
089993271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1708700174
Short name T414
Test name
Test status
Simulation time 28712804967 ps
CPU time 279.37 seconds
Started Aug 15 05:57:01 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 339596 kb
Host smart-a1e1fa61-a3fe-46ef-9acb-564cc3c2370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708700174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1708700174 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.3589458359
Short name T352
Test name
Test status
Simulation time 667863978 ps
CPU time 1.64 seconds
Started Aug 15 05:56:51 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 217340 kb
Host smart-ca7c9e61-b609-4825-9bc8-15192cc095f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589458359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3589458359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.3625146271
Short name T36
Test name
Test status
Simulation time 62522796 ps
CPU time 1.1 seconds
Started Aug 15 05:56:51 PM PDT 24
Finished Aug 15 05:56:52 PM PDT 24
Peak memory 219028 kb
Host smart-bf1c9ffe-b0cf-49f4-9702-76228e699aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625146271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3625146271 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.2918875496
Short name T220
Test name
Test status
Simulation time 16979754640 ps
CPU time 1745.78 seconds
Started Aug 15 05:56:51 PM PDT 24
Finished Aug 15 06:25:57 PM PDT 24
Peak memory 1233352 kb
Host smart-c66ce2ae-19be-456a-9659-a96973f47b51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918875496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.2918875496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2579796370
Short name T489
Test name
Test status
Simulation time 4054041429 ps
CPU time 57.99 seconds
Started Aug 15 05:56:58 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 273056 kb
Host smart-385e9c1e-0002-41dd-84a4-60d5244e71dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579796370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2579796370 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1343240365
Short name T316
Test name
Test status
Simulation time 9249730424 ps
CPU time 39.21 seconds
Started Aug 15 05:56:53 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 218024 kb
Host smart-67ea6fbd-4a41-4234-8e43-6681077dbf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343240365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1343240365 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_alert_test.1210915066
Short name T707
Test name
Test status
Simulation time 52129544 ps
CPU time 0.79 seconds
Started Aug 15 05:56:52 PM PDT 24
Finished Aug 15 05:56:53 PM PDT 24
Peak memory 204892 kb
Host smart-d174af06-4235-4883-be2f-507abe582dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210915066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1210915066 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_burst_write.8375476
Short name T540
Test name
Test status
Simulation time 27722576984 ps
CPU time 574.15 seconds
Started Aug 15 05:57:08 PM PDT 24
Finished Aug 15 06:06:43 PM PDT 24
Peak memory 245396 kb
Host smart-7fa54179-b433-4d7e-b570-f50820853698
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8375476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.8375476 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_error.1161230456
Short name T43
Test name
Test status
Simulation time 75707057948 ps
CPU time 130.42 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 05:59:13 PM PDT 24
Peak memory 322124 kb
Host smart-6c96f9ca-18aa-4cf1-bda6-59aaf976094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161230456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1161230456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.890656243
Short name T295
Test name
Test status
Simulation time 474679760 ps
CPU time 3.04 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 05:57:06 PM PDT 24
Peak memory 218492 kb
Host smart-eb0b3a41-913a-4a24-94e0-513a2128e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890656243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.890656243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1822360109
Short name T232
Test name
Test status
Simulation time 52746095 ps
CPU time 1.29 seconds
Started Aug 15 05:57:17 PM PDT 24
Finished Aug 15 05:57:18 PM PDT 24
Peak memory 216980 kb
Host smart-7bc2e1f2-b5dd-4be6-8489-0360976a9276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822360109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1822360109 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_sideload.972079738
Short name T472
Test name
Test status
Simulation time 68629767152 ps
CPU time 395.88 seconds
Started Aug 15 05:56:58 PM PDT 24
Finished Aug 15 06:03:34 PM PDT 24
Peak memory 565280 kb
Host smart-daf6b782-96bb-4df0-a071-b87bc14be87a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972079738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.972079738 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.2646072281
Short name T665
Test name
Test status
Simulation time 450270389 ps
CPU time 23.22 seconds
Started Aug 15 05:56:53 PM PDT 24
Finished Aug 15 05:57:16 PM PDT 24
Peak memory 217908 kb
Host smart-56389dac-8d4d-4406-ad7a-510409c1fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646072281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2646072281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.3768034920
Short name T296
Test name
Test status
Simulation time 26499572406 ps
CPU time 554.34 seconds
Started Aug 15 05:56:56 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 390824 kb
Host smart-953641cc-354c-4387-88bd-2582aa2cd9f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3768034920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3768034920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3228603807
Short name T263
Test name
Test status
Simulation time 64059840 ps
CPU time 0.8 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 05:56:08 PM PDT 24
Peak memory 204944 kb
Host smart-dbab4a86-afd9-43b7-b8f5-ec63bf23286f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228603807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3228603807 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.3972831077
Short name T524
Test name
Test status
Simulation time 15845175238 ps
CPU time 291.92 seconds
Started Aug 15 05:55:39 PM PDT 24
Finished Aug 15 06:00:31 PM PDT 24
Peak memory 497496 kb
Host smart-353f25d9-f273-4ab6-9eac-292f41a7d7a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972831077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3972831077 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1286700856
Short name T393
Test name
Test status
Simulation time 973523002 ps
CPU time 22.1 seconds
Started Aug 15 05:55:43 PM PDT 24
Finished Aug 15 05:56:05 PM PDT 24
Peak memory 224120 kb
Host smart-88d57268-7e37-4518-baa0-ada466820259
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286700856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.1286700856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.649047978
Short name T712
Test name
Test status
Simulation time 26071612423 ps
CPU time 549.23 seconds
Started Aug 15 05:55:42 PM PDT 24
Finished Aug 15 06:04:51 PM PDT 24
Peak memory 240100 kb
Host smart-b575767e-409e-4d52-924a-4d3b82e3be87
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649047978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.649047978 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2948027534
Short name T710
Test name
Test status
Simulation time 4637200472 ps
CPU time 27.49 seconds
Started Aug 15 05:55:36 PM PDT 24
Finished Aug 15 05:56:03 PM PDT 24
Peak memory 223548 kb
Host smart-cf5a0d43-22a9-4c3c-b5ab-7ef830fd5d5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2948027534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2948027534 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.63899357
Short name T664
Test name
Test status
Simulation time 1987459385 ps
CPU time 21.47 seconds
Started Aug 15 05:55:43 PM PDT 24
Finished Aug 15 05:56:05 PM PDT 24
Peak memory 218476 kb
Host smart-a7e980a4-7138-4b8a-aa63-d00764cdab8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=63899357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.63899357 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.2758127527
Short name T523
Test name
Test status
Simulation time 18214817938 ps
CPU time 59.26 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:57:05 PM PDT 24
Peak memory 218248 kb
Host smart-176f26cb-6e5b-4c99-a114-165dbba1b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758127527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2758127527 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.4195829549
Short name T624
Test name
Test status
Simulation time 32560086205 ps
CPU time 184.59 seconds
Started Aug 15 05:55:43 PM PDT 24
Finished Aug 15 05:58:47 PM PDT 24
Peak memory 369580 kb
Host smart-7c2a4f62-3c98-4cce-aa9d-3129b34d7aa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195829549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.41
95829549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.2436187740
Short name T481
Test name
Test status
Simulation time 17129323323 ps
CPU time 366.83 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 06:01:40 PM PDT 24
Peak memory 588284 kb
Host smart-960595b6-f389-4218-abd8-c65fbfa0a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436187740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2436187740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.136080206
Short name T253
Test name
Test status
Simulation time 749855648 ps
CPU time 4.03 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:55:37 PM PDT 24
Peak memory 217568 kb
Host smart-840b89e6-c52d-4a57-8abd-5b092b3d25e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136080206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.136080206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.3273058688
Short name T7
Test name
Test status
Simulation time 105420914 ps
CPU time 1.34 seconds
Started Aug 15 05:55:39 PM PDT 24
Finished Aug 15 05:55:40 PM PDT 24
Peak memory 223344 kb
Host smart-9a022972-e764-43f4-925e-8d7dad6257d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273058688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3273058688 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.544613253
Short name T196
Test name
Test status
Simulation time 150393868223 ps
CPU time 1853.02 seconds
Started Aug 15 05:55:44 PM PDT 24
Finished Aug 15 06:26:37 PM PDT 24
Peak memory 2036096 kb
Host smart-264de6fc-2711-4dc8-a2e0-88a5ddb9bbda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544613253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and
_output.544613253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3326817654
Short name T694
Test name
Test status
Simulation time 48475688800 ps
CPU time 127.94 seconds
Started Aug 15 05:55:36 PM PDT 24
Finished Aug 15 05:57:44 PM PDT 24
Peak memory 330996 kb
Host smart-464e8e49-3b20-4534-8d4f-3e617b392581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326817654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3326817654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sideload.1472051512
Short name T491
Test name
Test status
Simulation time 14817905560 ps
CPU time 107.18 seconds
Started Aug 15 05:55:36 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 313948 kb
Host smart-0c0e887b-6759-46a3-8548-8b69c668202d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472051512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1472051512 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.118865959
Short name T386
Test name
Test status
Simulation time 3164789031 ps
CPU time 55.49 seconds
Started Aug 15 05:55:38 PM PDT 24
Finished Aug 15 05:56:34 PM PDT 24
Peak memory 220544 kb
Host smart-fa6eff72-82f5-4676-9eae-c15069f51194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118865959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.118865959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3119546776
Short name T74
Test name
Test status
Simulation time 26205786818 ps
CPU time 1021.28 seconds
Started Aug 15 05:55:35 PM PDT 24
Finished Aug 15 06:12:37 PM PDT 24
Peak memory 1258828 kb
Host smart-88d5ccb2-a12b-4218-a4e1-db604813fc81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3119546776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3119546776 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.2043350129
Short name T658
Test name
Test status
Simulation time 97752709 ps
CPU time 1.7 seconds
Started Aug 15 05:55:32 PM PDT 24
Finished Aug 15 05:55:34 PM PDT 24
Peak memory 217772 kb
Host smart-f2f4ef0d-2685-4a2a-af08-1028b2a24121
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043350129 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.2043350129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3638011402
Short name T345
Test name
Test status
Simulation time 67254117 ps
CPU time 2.42 seconds
Started Aug 15 05:55:41 PM PDT 24
Finished Aug 15 05:55:44 PM PDT 24
Peak memory 217564 kb
Host smart-3f2a7f22-6f97-43fd-9f17-cee6dd9c32c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638011402 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3638011402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.3851209634
Short name T698
Test name
Test status
Simulation time 2922295286 ps
CPU time 38.01 seconds
Started Aug 15 05:55:38 PM PDT 24
Finished Aug 15 05:56:16 PM PDT 24
Peak memory 220568 kb
Host smart-f2466cae-d14e-4882-ba83-d69b2694d055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3851209634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3851209634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.424338715
Short name T633
Test name
Test status
Simulation time 620153471 ps
CPU time 32.85 seconds
Started Aug 15 05:55:31 PM PDT 24
Finished Aug 15 05:56:04 PM PDT 24
Peak memory 218792 kb
Host smart-9e7192c2-e036-47c0-b6e6-e1b06520c5b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=424338715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.424338715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.1892152053
Short name T82
Test name
Test status
Simulation time 506505416 ps
CPU time 24.49 seconds
Started Aug 15 05:55:31 PM PDT 24
Finished Aug 15 05:55:55 PM PDT 24
Peak memory 216952 kb
Host smart-792260fa-5122-422e-a4e1-3ea207474ca4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1892152053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1892152053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3262931384
Short name T285
Test name
Test status
Simulation time 1074763522 ps
CPU time 14.74 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:55:48 PM PDT 24
Peak memory 216968 kb
Host smart-438df164-cbc5-4ca6-9093-67282ab775fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3262931384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3262931384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3950980212
Short name T619
Test name
Test status
Simulation time 7223402703 ps
CPU time 180.46 seconds
Started Aug 15 05:55:43 PM PDT 24
Finished Aug 15 05:58:44 PM PDT 24
Peak memory 229372 kb
Host smart-e4499d35-31c6-4ad9-b9d6-2c8976eabd36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3950980212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3950980212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.1152715844
Short name T583
Test name
Test status
Simulation time 40523268480 ps
CPU time 140.59 seconds
Started Aug 15 05:55:33 PM PDT 24
Finished Aug 15 05:57:53 PM PDT 24
Peak memory 349888 kb
Host smart-2732c400-ad25-4936-9986-9f9fda651d84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1152715844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1152715844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.857970741
Short name T271
Test name
Test status
Simulation time 19222150 ps
CPU time 0.82 seconds
Started Aug 15 05:56:58 PM PDT 24
Finished Aug 15 05:56:59 PM PDT 24
Peak memory 204900 kb
Host smart-1d396b65-d01b-4785-96dc-d2fa05dc98e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857970741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.857970741 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3445256098
Short name T371
Test name
Test status
Simulation time 4128429664 ps
CPU time 219.22 seconds
Started Aug 15 05:57:01 PM PDT 24
Finished Aug 15 06:00:40 PM PDT 24
Peak memory 315140 kb
Host smart-defbbbf2-19bf-44f3-8116-2cab38a7a789
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445256098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3445256098 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.3776174300
Short name T638
Test name
Test status
Simulation time 8094442466 ps
CPU time 66.79 seconds
Started Aug 15 05:56:57 PM PDT 24
Finished Aug 15 05:58:04 PM PDT 24
Peak memory 218924 kb
Host smart-436d86a4-362c-4f43-bf41-5e2efc84a6da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776174300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.377617430
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2897075879
Short name T307
Test name
Test status
Simulation time 21979590123 ps
CPU time 299.84 seconds
Started Aug 15 05:56:55 PM PDT 24
Finished Aug 15 06:01:55 PM PDT 24
Peak memory 336776 kb
Host smart-74d8eac6-95a8-4f1a-9b2f-6af664aff9a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897075879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2
897075879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.907924813
Short name T265
Test name
Test status
Simulation time 7629180521 ps
CPU time 142.56 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 05:59:32 PM PDT 24
Peak memory 286428 kb
Host smart-d5c3f9be-2a0c-43d1-a689-de2e8f47664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907924813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.907924813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.929980856
Short name T64
Test name
Test status
Simulation time 7040830935 ps
CPU time 9.12 seconds
Started Aug 15 05:57:04 PM PDT 24
Finished Aug 15 05:57:13 PM PDT 24
Peak memory 217776 kb
Host smart-e94a3cee-c475-4559-8327-64db58c9c4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929980856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.929980856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.1791878013
Short name T394
Test name
Test status
Simulation time 59246598 ps
CPU time 1.44 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 05:57:11 PM PDT 24
Peak memory 223612 kb
Host smart-bf4e016a-cabd-4f76-a2d3-ae8f8ac66106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791878013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1791878013 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.3745855679
Short name T339
Test name
Test status
Simulation time 116678544480 ps
CPU time 1268.85 seconds
Started Aug 15 05:56:58 PM PDT 24
Finished Aug 15 06:18:07 PM PDT 24
Peak memory 1622796 kb
Host smart-0cd68707-3828-4162-99e0-55cfd3527a27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745855679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.3745855679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.3378078294
Short name T224
Test name
Test status
Simulation time 8010932802 ps
CPU time 170.93 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 05:59:54 PM PDT 24
Peak memory 366420 kb
Host smart-a602c0a3-b228-44e9-a65f-566d3ac4bf47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378078294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3378078294 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.82603027
Short name T219
Test name
Test status
Simulation time 10936743769 ps
CPU time 28.29 seconds
Started Aug 15 05:57:04 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 218056 kb
Host smart-c0a5637d-86fb-4e21-bc58-7b45a13a5e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82603027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.82603027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1709797031
Short name T78
Test name
Test status
Simulation time 42647148786 ps
CPU time 969.52 seconds
Started Aug 15 05:56:54 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 862876 kb
Host smart-191477dd-1089-4732-b8e6-153ce768dfb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1709797031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1709797031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2820515523
Short name T599
Test name
Test status
Simulation time 15700182 ps
CPU time 0.82 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 05:57:03 PM PDT 24
Peak memory 204940 kb
Host smart-69c86ee5-8cb6-468c-b812-be0d9b42cbdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820515523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2820515523 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2019877510
Short name T245
Test name
Test status
Simulation time 43209750051 ps
CPU time 106.25 seconds
Started Aug 15 05:57:05 PM PDT 24
Finished Aug 15 05:58:52 PM PDT 24
Peak memory 310456 kb
Host smart-21cdb632-7416-4675-b029-d3d9e17a46c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019877510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2019877510 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.1701746434
Short name T171
Test name
Test status
Simulation time 7230496102 ps
CPU time 657.9 seconds
Started Aug 15 05:56:57 PM PDT 24
Finished Aug 15 06:07:56 PM PDT 24
Peak memory 239384 kb
Host smart-ab8bb6ea-210e-4eea-87fc-562f04bb1eac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701746434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.170174643
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.2665467204
Short name T537
Test name
Test status
Simulation time 7428768466 ps
CPU time 137.91 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 05:59:27 PM PDT 24
Peak memory 335600 kb
Host smart-1aea10db-f414-48ab-8edf-194217f54ea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665467204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2
665467204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.3258966077
Short name T324
Test name
Test status
Simulation time 11635600156 ps
CPU time 269.27 seconds
Started Aug 15 05:57:06 PM PDT 24
Finished Aug 15 06:01:35 PM PDT 24
Peak memory 484760 kb
Host smart-99f41bdb-41ca-45f4-b464-06c1a2a937b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258966077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3258966077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.1101609497
Short name T644
Test name
Test status
Simulation time 1713023750 ps
CPU time 6.77 seconds
Started Aug 15 05:56:59 PM PDT 24
Finished Aug 15 05:57:06 PM PDT 24
Peak memory 217384 kb
Host smart-f01e8810-6dfa-4440-9695-45af094dda24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101609497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1101609497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.187222379
Short name T8
Test name
Test status
Simulation time 602585779 ps
CPU time 1.82 seconds
Started Aug 15 05:57:01 PM PDT 24
Finished Aug 15 05:57:03 PM PDT 24
Peak memory 223572 kb
Host smart-877f69ac-d96e-46f3-9363-5c6a2a0970e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187222379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.187222379 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.2873976438
Short name T16
Test name
Test status
Simulation time 60077622266 ps
CPU time 2408.7 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 06:37:18 PM PDT 24
Peak memory 2481176 kb
Host smart-dce2812f-eb75-49bb-8a0b-8273321bab1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873976438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.2873976438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.250490064
Short name T677
Test name
Test status
Simulation time 11282634572 ps
CPU time 220.32 seconds
Started Aug 15 05:56:53 PM PDT 24
Finished Aug 15 06:00:33 PM PDT 24
Peak memory 315556 kb
Host smart-68af4676-7b67-47b8-b4a7-6c8681f6b768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250490064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.250490064 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.2579661563
Short name T436
Test name
Test status
Simulation time 228319711 ps
CPU time 1.15 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:57:14 PM PDT 24
Peak memory 217968 kb
Host smart-8300644d-b155-46a9-a407-0a99786fd7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579661563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2579661563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.1174124043
Short name T333
Test name
Test status
Simulation time 6450537639 ps
CPU time 42.01 seconds
Started Aug 15 05:57:06 PM PDT 24
Finished Aug 15 05:57:49 PM PDT 24
Peak memory 255020 kb
Host smart-ea33e8ed-f8ca-4037-913d-9a0baadf718b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1174124043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1174124043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_alert_test.233285531
Short name T528
Test name
Test status
Simulation time 16485437 ps
CPU time 0.82 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 05:57:10 PM PDT 24
Peak memory 204896 kb
Host smart-ec3ddf4b-7955-44e5-a994-a0ff4778b35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233285531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.233285531 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2621130137
Short name T194
Test name
Test status
Simulation time 4177987385 ps
CPU time 210.05 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 06:00:32 PM PDT 24
Peak memory 318476 kb
Host smart-fdf3c067-a1fb-4af9-8976-89f931294e59
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621130137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2621130137 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.1735890143
Short name T703
Test name
Test status
Simulation time 8405082380 ps
CPU time 780.28 seconds
Started Aug 15 05:57:12 PM PDT 24
Finished Aug 15 06:10:12 PM PDT 24
Peak memory 242944 kb
Host smart-87e17ff9-b51b-4820-bc00-d20d3f551639
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735890143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.173589014
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1058074202
Short name T268
Test name
Test status
Simulation time 25739156620 ps
CPU time 146.7 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 05:59:30 PM PDT 24
Peak memory 333940 kb
Host smart-21642be6-ee95-4349-be96-24bf1e5af642
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058074202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1
058074202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.289437524
Short name T299
Test name
Test status
Simulation time 3662908046 ps
CPU time 280 seconds
Started Aug 15 05:57:04 PM PDT 24
Finished Aug 15 06:01:44 PM PDT 24
Peak memory 346724 kb
Host smart-991449be-5ab7-4cd6-977b-837745314d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289437524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.289437524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.881131562
Short name T412
Test name
Test status
Simulation time 320041282 ps
CPU time 2.11 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 05:57:11 PM PDT 24
Peak memory 217380 kb
Host smart-d6e69c08-07ce-4d2b-aede-81e6ae4a0a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881131562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.881131562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.4173273082
Short name T86
Test name
Test status
Simulation time 50190206 ps
CPU time 1.36 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 05:57:04 PM PDT 24
Peak memory 219044 kb
Host smart-7ce581d2-fed7-4061-85a6-b74ab3a0cbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173273082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.4173273082 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.3597443945
Short name T469
Test name
Test status
Simulation time 43723541289 ps
CPU time 1103.15 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 06:15:27 PM PDT 24
Peak memory 870188 kb
Host smart-52e6bad8-40d2-46cd-882e-0465984f608e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597443945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.3597443945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.1598889401
Short name T231
Test name
Test status
Simulation time 28063878051 ps
CPU time 179.65 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 06:00:03 PM PDT 24
Peak memory 370876 kb
Host smart-98bb1425-2d22-4542-8d10-6a2d8eb2240e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598889401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1598889401 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.3345253461
Short name T400
Test name
Test status
Simulation time 2935447168 ps
CPU time 53.26 seconds
Started Aug 15 05:57:05 PM PDT 24
Finished Aug 15 05:57:59 PM PDT 24
Peak memory 219064 kb
Host smart-d1ac2729-e4d4-4d50-842d-577f9650889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345253461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3345253461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2435912583
Short name T294
Test name
Test status
Simulation time 26338514982 ps
CPU time 629.35 seconds
Started Aug 15 05:57:06 PM PDT 24
Finished Aug 15 06:07:36 PM PDT 24
Peak memory 485944 kb
Host smart-dac5672b-512d-4544-8b15-861eb7dd1fa0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2435912583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2435912583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_alert_test.871181180
Short name T370
Test name
Test status
Simulation time 18090463 ps
CPU time 0.79 seconds
Started Aug 15 05:57:06 PM PDT 24
Finished Aug 15 05:57:06 PM PDT 24
Peak memory 204940 kb
Host smart-9eca69f4-83b4-41db-9314-ffadcfc35246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871181180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.871181180 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2243742031
Short name T346
Test name
Test status
Simulation time 9857009899 ps
CPU time 276.23 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 449856 kb
Host smart-136d71b3-5175-4ac7-9ef0-e2afe226e186
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243742031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2243742031 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.4138526284
Short name T277
Test name
Test status
Simulation time 30111754331 ps
CPU time 547.49 seconds
Started Aug 15 05:57:01 PM PDT 24
Finished Aug 15 06:06:09 PM PDT 24
Peak memory 248244 kb
Host smart-7c832874-4e3a-44c1-acc8-a3a58768344b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138526284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.413852628
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.31227545
Short name T676
Test name
Test status
Simulation time 6501804157 ps
CPU time 64.11 seconds
Started Aug 15 05:56:59 PM PDT 24
Finished Aug 15 05:58:03 PM PDT 24
Peak memory 247840 kb
Host smart-af5049fc-de7c-4e03-a6fe-c6cff7205d3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31227545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.312
27545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_key_error.4246358749
Short name T510
Test name
Test status
Simulation time 5696701094 ps
CPU time 7.96 seconds
Started Aug 15 05:57:00 PM PDT 24
Finished Aug 15 05:57:08 PM PDT 24
Peak memory 217836 kb
Host smart-5f29831c-5815-42f2-8d97-7fc4d6de8dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246358749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.4246358749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.2244109012
Short name T282
Test name
Test status
Simulation time 36078534 ps
CPU time 1.31 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:57:15 PM PDT 24
Peak memory 217028 kb
Host smart-2eaf1121-ccae-421f-90ec-6ca012ad138e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244109012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2244109012 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.1467842460
Short name T442
Test name
Test status
Simulation time 70250844072 ps
CPU time 4364.1 seconds
Started Aug 15 05:57:01 PM PDT 24
Finished Aug 15 07:09:46 PM PDT 24
Peak memory 3452516 kb
Host smart-1cd207fd-f1d8-4b5a-9fd5-c6befdb51940
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467842460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.1467842460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.514342038
Short name T77
Test name
Test status
Simulation time 14186123433 ps
CPU time 207.43 seconds
Started Aug 15 05:57:00 PM PDT 24
Finished Aug 15 06:00:28 PM PDT 24
Peak memory 400868 kb
Host smart-213c89dc-aa99-48e9-8205-de0736189b93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514342038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.514342038 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1444405276
Short name T645
Test name
Test status
Simulation time 103221644 ps
CPU time 2.01 seconds
Started Aug 15 05:57:01 PM PDT 24
Finished Aug 15 05:57:03 PM PDT 24
Peak memory 217696 kb
Host smart-b344a703-dc31-4b4d-8418-c0c57f858952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444405276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1444405276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2818840202
Short name T170
Test name
Test status
Simulation time 6986779112 ps
CPU time 540.66 seconds
Started Aug 15 05:57:11 PM PDT 24
Finished Aug 15 06:06:12 PM PDT 24
Peak memory 332352 kb
Host smart-bdc90424-aeb9-46b9-9ad5-d81dc77e6d4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2818840202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2818840202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_alert_test.3521408760
Short name T502
Test name
Test status
Simulation time 20599939 ps
CPU time 0.86 seconds
Started Aug 15 05:57:05 PM PDT 24
Finished Aug 15 05:57:05 PM PDT 24
Peak memory 204856 kb
Host smart-3e8dcc3c-41e9-4248-b098-836efecb22b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521408760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3521408760 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.3051490403
Short name T243
Test name
Test status
Simulation time 10573680443 ps
CPU time 243.02 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 06:01:13 PM PDT 24
Peak memory 427776 kb
Host smart-db64a3ca-f879-4dec-8842-2be0be37a9e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051490403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3051490403 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.266679486
Short name T209
Test name
Test status
Simulation time 65457850974 ps
CPU time 612.77 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 243224 kb
Host smart-85b1e575-b93b-4b64-8e16-f642f2bc7409
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266679486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.266679486
+enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.3169120499
Short name T308
Test name
Test status
Simulation time 1557787815 ps
CPU time 36.46 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 247576 kb
Host smart-1dbd3175-68e3-42c2-b3df-254503c2ac29
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169120499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3
169120499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.3218822734
Short name T29
Test name
Test status
Simulation time 44475164149 ps
CPU time 280.13 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 06:01:54 PM PDT 24
Peak memory 474432 kb
Host smart-0f2a3b9e-a7b7-4043-943d-fec1a7007d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218822734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3218822734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.99473401
Short name T240
Test name
Test status
Simulation time 1411730880 ps
CPU time 7.9 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 05:57:10 PM PDT 24
Peak memory 217396 kb
Host smart-c1a1e2c9-64f9-4287-8ae4-ca248c62a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99473401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.99473401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.3430603996
Short name T424
Test name
Test status
Simulation time 59788758 ps
CPU time 1.32 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 05:57:04 PM PDT 24
Peak memory 223104 kb
Host smart-b44462a8-d371-44d7-9531-c7a66a95dcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430603996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3430603996 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.3525779397
Short name T76
Test name
Test status
Simulation time 65612847411 ps
CPU time 599.09 seconds
Started Aug 15 05:57:00 PM PDT 24
Finished Aug 15 06:07:00 PM PDT 24
Peak memory 960284 kb
Host smart-b5986071-3de1-4cd1-9477-e442f1c5b439
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525779397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.3525779397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2630080763
Short name T18
Test name
Test status
Simulation time 53441803580 ps
CPU time 311.52 seconds
Started Aug 15 05:57:00 PM PDT 24
Finished Aug 15 06:02:12 PM PDT 24
Peak memory 495364 kb
Host smart-53b1bd03-6629-4117-8b5e-f1af46e69a48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630080763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2630080763 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3281283510
Short name T67
Test name
Test status
Simulation time 11894511422 ps
CPU time 73.73 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 05:58:24 PM PDT 24
Peak memory 222264 kb
Host smart-15b3d713-885d-4d73-9beb-7608df4ac5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281283510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3281283510 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.4103840501
Short name T377
Test name
Test status
Simulation time 112135596757 ps
CPU time 2062.08 seconds
Started Aug 15 05:57:03 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 1064932 kb
Host smart-fdf680d8-9020-4789-98cd-8b7bd68ff3eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4103840501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4103840501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_alert_test.2620185780
Short name T702
Test name
Test status
Simulation time 39271243 ps
CPU time 0.81 seconds
Started Aug 15 05:57:08 PM PDT 24
Finished Aug 15 05:57:08 PM PDT 24
Peak memory 204916 kb
Host smart-82b3d17c-ed1c-427f-afe0-123d77851c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620185780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2620185780 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3511065046
Short name T157
Test name
Test status
Simulation time 35392623111 ps
CPU time 345.74 seconds
Started Aug 15 05:57:07 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 515348 kb
Host smart-39fc629b-640f-4400-9d00-fb4add5e83c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511065046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3511065046 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.2750287460
Short name T490
Test name
Test status
Simulation time 19589433418 ps
CPU time 349.66 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 06:02:52 PM PDT 24
Peak memory 232316 kb
Host smart-c719ff09-87d3-4dd7-99a9-432b8bd43a28
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750287460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.275028746
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1667233788
Short name T443
Test name
Test status
Simulation time 30546866623 ps
CPU time 116.2 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 05:59:06 PM PDT 24
Peak memory 310480 kb
Host smart-7532cd81-a03a-4143-baad-b892119a42a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667233788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
667233788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.2055969437
Short name T28
Test name
Test status
Simulation time 4046360134 ps
CPU time 151.58 seconds
Started Aug 15 05:57:08 PM PDT 24
Finished Aug 15 05:59:40 PM PDT 24
Peak memory 299904 kb
Host smart-fe56612f-c74e-43b2-8959-27cfdef4efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055969437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2055969437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.4217073163
Short name T533
Test name
Test status
Simulation time 5832591907 ps
CPU time 9.02 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 05:57:19 PM PDT 24
Peak memory 217708 kb
Host smart-f4bda59c-d486-4be2-b20f-6e3271bc5df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217073163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.4217073163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.2800562685
Short name T572
Test name
Test status
Simulation time 97777734 ps
CPU time 1.49 seconds
Started Aug 15 05:57:11 PM PDT 24
Finished Aug 15 05:57:13 PM PDT 24
Peak memory 217516 kb
Host smart-d2a22a8d-f7b7-44a3-b897-e1a80b27309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800562685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2800562685 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3832889574
Short name T666
Test name
Test status
Simulation time 38792658778 ps
CPU time 2097.64 seconds
Started Aug 15 05:57:11 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 1338632 kb
Host smart-d84482c7-1a0e-4518-80eb-b2290e3f2831
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832889574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3832889574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.1059871438
Short name T475
Test name
Test status
Simulation time 5157004174 ps
CPU time 375.84 seconds
Started Aug 15 05:57:11 PM PDT 24
Finished Aug 15 06:03:27 PM PDT 24
Peak memory 399904 kb
Host smart-9bad063b-94b5-4089-abfc-64bca12a7c5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059871438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1059871438 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.4156039128
Short name T351
Test name
Test status
Simulation time 138238160 ps
CPU time 2.29 seconds
Started Aug 15 05:57:02 PM PDT 24
Finished Aug 15 05:57:05 PM PDT 24
Peak memory 218012 kb
Host smart-3bd8f555-12d3-432f-8c6e-bcce5adb2ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156039128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.4156039128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.2610084643
Short name T439
Test name
Test status
Simulation time 357302023 ps
CPU time 6.91 seconds
Started Aug 15 05:57:08 PM PDT 24
Finished Aug 15 05:57:15 PM PDT 24
Peak memory 218876 kb
Host smart-8a4f5fe2-2e3c-4ea1-8816-012ecc1f197b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2610084643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2610084643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_alert_test.2527077960
Short name T326
Test name
Test status
Simulation time 23022802 ps
CPU time 0.74 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 05:57:11 PM PDT 24
Peak memory 204900 kb
Host smart-fa056ac7-0582-4923-8eea-4f9fa81678ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527077960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2527077960 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.2796473202
Short name T283
Test name
Test status
Simulation time 6674818328 ps
CPU time 170.31 seconds
Started Aug 15 05:57:12 PM PDT 24
Finished Aug 15 06:00:03 PM PDT 24
Peak memory 372600 kb
Host smart-52ff9d43-0c7b-4242-83ac-43e32c70c3c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796473202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2796473202 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.957380480
Short name T453
Test name
Test status
Simulation time 6291558738 ps
CPU time 611.34 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 237228 kb
Host smart-956f0f83-4469-4a8c-b330-f5a704845eeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957380480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.957380480
+enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.114365889
Short name T480
Test name
Test status
Simulation time 37013874790 ps
CPU time 103.05 seconds
Started Aug 15 05:57:08 PM PDT 24
Finished Aug 15 05:58:51 PM PDT 24
Peak memory 308864 kb
Host smart-136f0623-a245-449b-8b50-f1c911f31a5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114365889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.11
4365889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.127836735
Short name T303
Test name
Test status
Simulation time 4963327915 ps
CPU time 115.78 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 05:59:05 PM PDT 24
Peak memory 331088 kb
Host smart-2e385399-80cc-47b1-8bed-81ea76c45eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127836735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.127836735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.2975082579
Short name T60
Test name
Test status
Simulation time 309804247 ps
CPU time 1.91 seconds
Started Aug 15 05:57:14 PM PDT 24
Finished Aug 15 05:57:16 PM PDT 24
Peak memory 217296 kb
Host smart-84b418cb-4155-42bc-b03b-6f11e0f1d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975082579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2975082579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1924713220
Short name T274
Test name
Test status
Simulation time 37445888075 ps
CPU time 2245.8 seconds
Started Aug 15 05:57:14 PM PDT 24
Finished Aug 15 06:34:41 PM PDT 24
Peak memory 1385176 kb
Host smart-cb7c89dd-ed43-4682-8a21-ad6fbaeb5048
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924713220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1924713220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.2592468470
Short name T486
Test name
Test status
Simulation time 37621929019 ps
CPU time 431.43 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 06:04:22 PM PDT 24
Peak memory 592964 kb
Host smart-2761f7c0-5ec7-40c1-a4ab-8b97222ae00a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592468470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2592468470 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1207394500
Short name T521
Test name
Test status
Simulation time 19564754837 ps
CPU time 58.72 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:58:12 PM PDT 24
Peak memory 223896 kb
Host smart-a7145c68-d273-4d8f-80b1-99ca170079fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207394500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1207394500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.236734113
Short name T482
Test name
Test status
Simulation time 3492595595 ps
CPU time 13.41 seconds
Started Aug 15 05:57:08 PM PDT 24
Finished Aug 15 05:57:21 PM PDT 24
Peak memory 220972 kb
Host smart-0dce7da3-ecc0-4a27-abc0-8e7ef8f71af8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=236734113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.236734113 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_alert_test.462543821
Short name T215
Test name
Test status
Simulation time 216015342 ps
CPU time 0.86 seconds
Started Aug 15 05:57:14 PM PDT 24
Finished Aug 15 05:57:15 PM PDT 24
Peak memory 204928 kb
Host smart-2bd2d2e3-88d9-41ae-9678-9c5510cd5f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462543821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.462543821 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.576996765
Short name T356
Test name
Test status
Simulation time 29740720785 ps
CPU time 49.96 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:58:04 PM PDT 24
Peak memory 261036 kb
Host smart-4b19caba-9167-4998-b18e-4d2154130bf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576996765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.576996765 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.2248518011
Short name T628
Test name
Test status
Simulation time 2043454567 ps
CPU time 74.81 seconds
Started Aug 15 05:57:12 PM PDT 24
Finished Aug 15 05:58:27 PM PDT 24
Peak memory 222188 kb
Host smart-dfc29f41-092c-4c89-9da3-346b71aae8a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248518011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.224851801
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.914208488
Short name T464
Test name
Test status
Simulation time 50154508293 ps
CPU time 106.76 seconds
Started Aug 15 05:57:12 PM PDT 24
Finished Aug 15 05:58:59 PM PDT 24
Peak memory 264948 kb
Host smart-7d581083-beb6-4e30-ac77-686ea504c795
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914208488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.91
4208488 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.2658736560
Short name T328
Test name
Test status
Simulation time 19845763593 ps
CPU time 302.9 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 06:02:18 PM PDT 24
Peak memory 358876 kb
Host smart-2706e1d7-8ef7-4686-8b54-a5f7ba8846ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658736560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2658736560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1620757865
Short name T562
Test name
Test status
Simulation time 215374824 ps
CPU time 1.93 seconds
Started Aug 15 05:57:06 PM PDT 24
Finished Aug 15 05:57:08 PM PDT 24
Peak memory 217340 kb
Host smart-98218a29-2136-4081-8297-58323b2a4728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620757865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1620757865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.2907071843
Short name T9
Test name
Test status
Simulation time 46821225 ps
CPU time 1.24 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 05:57:11 PM PDT 24
Peak memory 223540 kb
Host smart-28216b53-3229-488b-9241-3ca83291c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907071843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2907071843 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3351562560
Short name T427
Test name
Test status
Simulation time 13810468332 ps
CPU time 1397.11 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 06:20:26 PM PDT 24
Peak memory 1043764 kb
Host smart-29c57a29-864b-422b-bf7b-ae3153604cc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351562560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3351562560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.1332486603
Short name T509
Test name
Test status
Simulation time 19363098704 ps
CPU time 436.28 seconds
Started Aug 15 05:57:16 PM PDT 24
Finished Aug 15 06:04:32 PM PDT 24
Peak memory 601972 kb
Host smart-781c1b00-5223-4436-ba94-7cc05ca9c2c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332486603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1332486603 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.1644719452
Short name T270
Test name
Test status
Simulation time 621723691 ps
CPU time 11.15 seconds
Started Aug 15 05:57:14 PM PDT 24
Finished Aug 15 05:57:25 PM PDT 24
Peak memory 218124 kb
Host smart-f0bd16ad-eb35-4438-95ab-21a6d3b5319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644719452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1644719452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.3313653388
Short name T706
Test name
Test status
Simulation time 111049375863 ps
CPU time 788.36 seconds
Started Aug 15 05:57:16 PM PDT 24
Finished Aug 15 06:10:25 PM PDT 24
Peak memory 1084320 kb
Host smart-c25af6f9-ff32-4b2e-aec2-e10f0503c7c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3313653388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3313653388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_alert_test.724674697
Short name T548
Test name
Test status
Simulation time 14452936 ps
CPU time 0.81 seconds
Started Aug 15 05:57:12 PM PDT 24
Finished Aug 15 05:57:13 PM PDT 24
Peak memory 204892 kb
Host smart-06f52594-6236-442c-a3a3-5c0c59471de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724674697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.724674697 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.634633377
Short name T361
Test name
Test status
Simulation time 732314168 ps
CPU time 18.38 seconds
Started Aug 15 05:57:14 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 240104 kb
Host smart-7373820e-4a31-4fab-9059-b1bc00c2dba5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634633377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.634633377 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.668392315
Short name T318
Test name
Test status
Simulation time 36068989389 ps
CPU time 929.96 seconds
Started Aug 15 05:57:16 PM PDT 24
Finished Aug 15 06:12:46 PM PDT 24
Peak memory 255804 kb
Host smart-98ffa67c-a3d2-4338-9904-2ce7567984be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668392315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.668392315
+enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.2834066382
Short name T269
Test name
Test status
Simulation time 23429624178 ps
CPU time 255.26 seconds
Started Aug 15 05:57:08 PM PDT 24
Finished Aug 15 06:01:23 PM PDT 24
Peak memory 436520 kb
Host smart-abd86e00-a50f-4cb3-a0ce-154e68b52237
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834066382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2
834066382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.1341738599
Short name T226
Test name
Test status
Simulation time 1739363897 ps
CPU time 40.08 seconds
Started Aug 15 05:57:16 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 271980 kb
Host smart-5ae5d3fe-0c0b-4883-bab5-146fb359db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341738599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1341738599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.2067401409
Short name T678
Test name
Test status
Simulation time 3593596551 ps
CPU time 6.97 seconds
Started Aug 15 05:57:07 PM PDT 24
Finished Aug 15 05:57:14 PM PDT 24
Peak memory 217788 kb
Host smart-efad652a-81e6-447e-a151-36bad3b6f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067401409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2067401409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.440380457
Short name T722
Test name
Test status
Simulation time 81185577 ps
CPU time 1.28 seconds
Started Aug 15 05:57:11 PM PDT 24
Finished Aug 15 05:57:13 PM PDT 24
Peak memory 218660 kb
Host smart-7301079c-2b07-4d5a-a492-a37db3967b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440380457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.440380457 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.2439776002
Short name T458
Test name
Test status
Simulation time 64226217480 ps
CPU time 3632.94 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 06:57:48 PM PDT 24
Peak memory 3182620 kb
Host smart-44c0bbfe-9e2f-454e-b323-3bc6e03f1fcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439776002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.2439776002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.253317156
Short name T641
Test name
Test status
Simulation time 2181857825 ps
CPU time 86.52 seconds
Started Aug 15 05:57:10 PM PDT 24
Finished Aug 15 05:58:37 PM PDT 24
Peak memory 256252 kb
Host smart-29664d12-741d-4065-9979-94cb852ba30a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253317156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.253317156 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.2554445716
Short name T261
Test name
Test status
Simulation time 24727805017 ps
CPU time 53.23 seconds
Started Aug 15 05:57:16 PM PDT 24
Finished Aug 15 05:58:09 PM PDT 24
Peak memory 218996 kb
Host smart-609639b8-a127-4ca1-915f-a0374f75024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554445716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2554445716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.2802298914
Short name T254
Test name
Test status
Simulation time 57391408643 ps
CPU time 417.6 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 06:04:07 PM PDT 24
Peak memory 593224 kb
Host smart-2591aada-7426-4222-80c1-e07e3a241b16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2802298914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2802298914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1414190597
Short name T46
Test name
Test status
Simulation time 87083668 ps
CPU time 0.76 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:57:14 PM PDT 24
Peak memory 204928 kb
Host smart-8163dc59-c85f-42c3-8e49-33099715900c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414190597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1414190597 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.2625001775
Short name T183
Test name
Test status
Simulation time 26689812522 ps
CPU time 204.85 seconds
Started Aug 15 05:57:11 PM PDT 24
Finished Aug 15 06:00:36 PM PDT 24
Peak memory 377540 kb
Host smart-55fd5099-4927-4d18-8dc4-22739aba4933
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625001775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2625001775 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.3048340666
Short name T68
Test name
Test status
Simulation time 12795589275 ps
CPU time 536.93 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 06:06:10 PM PDT 24
Peak memory 240628 kb
Host smart-8794f400-e780-452f-a978-7535b51c2d9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048340666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.304834066
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.1648313227
Short name T323
Test name
Test status
Simulation time 75714009556 ps
CPU time 106.96 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 05:59:02 PM PDT 24
Peak memory 323108 kb
Host smart-08a3757f-118d-4a81-99f6-79b70e348fd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648313227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1
648313227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.2286941493
Short name T515
Test name
Test status
Simulation time 34899392384 ps
CPU time 289.91 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 06:02:06 PM PDT 24
Peak memory 345296 kb
Host smart-6dbd53bd-6a84-40e9-9978-e49bb5add34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286941493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2286941493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.65828554
Short name T247
Test name
Test status
Simulation time 774220958 ps
CPU time 4.22 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:57:18 PM PDT 24
Peak memory 218384 kb
Host smart-2bd038d3-f7a1-4b4d-96f1-ce9bbbe9375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65828554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.65828554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.492725563
Short name T235
Test name
Test status
Simulation time 87256429 ps
CPU time 1.27 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 05:57:17 PM PDT 24
Peak memory 218456 kb
Host smart-bfa3a80e-f8af-4c47-a024-39d874551fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492725563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.492725563 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.3387172292
Short name T646
Test name
Test status
Simulation time 14250544644 ps
CPU time 1478.46 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 06:21:52 PM PDT 24
Peak memory 1086860 kb
Host smart-8009ef7c-7129-450c-9888-db236867b2c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387172292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.3387172292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.250258901
Short name T588
Test name
Test status
Simulation time 6830947555 ps
CPU time 162.77 seconds
Started Aug 15 05:57:14 PM PDT 24
Finished Aug 15 05:59:57 PM PDT 24
Peak memory 349928 kb
Host smart-2c11b2a2-11f2-4a9f-8312-cc7c586be3ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250258901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.250258901 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1566329091
Short name T648
Test name
Test status
Simulation time 279850658 ps
CPU time 14.27 seconds
Started Aug 15 05:57:09 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 218048 kb
Host smart-d37a04b9-964e-4e25-b2a9-e71a82a2a355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566329091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1566329091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.3263025652
Short name T317
Test name
Test status
Simulation time 2445441782 ps
CPU time 97.98 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 05:58:53 PM PDT 24
Peak memory 257084 kb
Host smart-fee749c3-8b6b-4940-af8b-edca8d0bd2c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3263025652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3263025652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1111532278
Short name T552
Test name
Test status
Simulation time 45067378 ps
CPU time 0.8 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:09 PM PDT 24
Peak memory 204912 kb
Host smart-ec0439f0-0a5d-446a-ad0e-5d327d1067ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111532278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1111532278 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.948370146
Short name T642
Test name
Test status
Simulation time 36988628124 ps
CPU time 240.9 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 06:00:00 PM PDT 24
Peak memory 403180 kb
Host smart-aa85681f-b791-47bf-877e-25f266bc02a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948370146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.948370146 +enable_masking=0
+sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.433989343
Short name T512
Test name
Test status
Simulation time 13739564305 ps
CPU time 296.28 seconds
Started Aug 15 05:56:02 PM PDT 24
Finished Aug 15 06:00:58 PM PDT 24
Peak memory 453288 kb
Host smart-26bd9284-057c-40ae-ad2f-4fd2f1ee335c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433989343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_part
ial_data.433989343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.2596438810
Short name T358
Test name
Test status
Simulation time 76442795017 ps
CPU time 589.29 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 06:05:51 PM PDT 24
Peak memory 244876 kb
Host smart-fe4ca50e-6027-4c6c-bd37-9a80d6a02c32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596438810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2596438810
+enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1317156400
Short name T474
Test name
Test status
Simulation time 675918806 ps
CPU time 13.48 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 05:56:13 PM PDT 24
Peak memory 220536 kb
Host smart-424a932f-7555-4102-b3a2-4d663457997c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1317156400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1317156400 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.488254572
Short name T635
Test name
Test status
Simulation time 733380114 ps
CPU time 5.47 seconds
Started Aug 15 05:55:43 PM PDT 24
Finished Aug 15 05:55:49 PM PDT 24
Peak memory 215364 kb
Host smart-8ac9b9c7-91f8-45bf-8804-a637120f6f74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=488254572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.488254572 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2790814183
Short name T14
Test name
Test status
Simulation time 6874262548 ps
CPU time 39.46 seconds
Started Aug 15 05:55:42 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 218376 kb
Host smart-e86c4e44-6017-4b22-aa6b-5d2368e48765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790814183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2790814183 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.707008676
Short name T432
Test name
Test status
Simulation time 15136360319 ps
CPU time 105.36 seconds
Started Aug 15 05:55:45 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 300240 kb
Host smart-9867e15c-1ce5-4790-aa36-a264707410fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707008676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.707
008676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.552962572
Short name T387
Test name
Test status
Simulation time 726764489 ps
CPU time 45.97 seconds
Started Aug 15 05:55:42 PM PDT 24
Finished Aug 15 05:56:28 PM PDT 24
Peak memory 248532 kb
Host smart-b2c5276d-a655-4053-ae81-d9f2248997da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552962572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.552962572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3572681988
Short name T620
Test name
Test status
Simulation time 1723651197 ps
CPU time 3.49 seconds
Started Aug 15 05:55:49 PM PDT 24
Finished Aug 15 05:55:52 PM PDT 24
Peak memory 217840 kb
Host smart-b70605c3-4e68-4f1b-bc1a-2717bfad0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572681988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3572681988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.1734105101
Short name T385
Test name
Test status
Simulation time 53666077 ps
CPU time 1.4 seconds
Started Aug 15 05:56:14 PM PDT 24
Finished Aug 15 05:56:16 PM PDT 24
Peak memory 217628 kb
Host smart-97c33d00-afd0-4889-aba3-58e95960f04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734105101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1734105101 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.446297262
Short name T591
Test name
Test status
Simulation time 140886844872 ps
CPU time 4007.14 seconds
Started Aug 15 05:55:54 PM PDT 24
Finished Aug 15 07:02:42 PM PDT 24
Peak memory 3477920 kb
Host smart-8571d300-87be-4be6-ab72-f078ee46b6e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446297262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and
_output.446297262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.229789719
Short name T80
Test name
Test status
Simulation time 6370430411 ps
CPU time 180.62 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 05:59:11 PM PDT 24
Peak memory 391648 kb
Host smart-de79d6f6-f128-4db7-ac67-c40c99381205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229789719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.229789719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.1663952557
Short name T208
Test name
Test status
Simulation time 3850782217 ps
CPU time 110.68 seconds
Started Aug 15 05:55:45 PM PDT 24
Finished Aug 15 05:57:35 PM PDT 24
Peak memory 318508 kb
Host smart-2a2541c0-7100-4008-8060-a19be209922b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663952557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1663952557 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.3153817709
Short name T380
Test name
Test status
Simulation time 651895548 ps
CPU time 17.46 seconds
Started Aug 15 05:56:00 PM PDT 24
Finished Aug 15 05:56:17 PM PDT 24
Peak memory 218016 kb
Host smart-59cdb9e9-ef28-4794-9ae3-1e469d8b7b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153817709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3153817709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.2226521030
Short name T257
Test name
Test status
Simulation time 58239422271 ps
CPU time 1967.43 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 06:28:48 PM PDT 24
Peak memory 1236852 kb
Host smart-6f6e1cf8-6cab-478b-9ab9-4aada78dfbe0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2226521030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2226521030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_alert_test.971913276
Short name T246
Test name
Test status
Simulation time 16605741 ps
CPU time 0.8 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 05:56:00 PM PDT 24
Peak memory 204904 kb
Host smart-0f453808-e1a4-447d-acd0-346a92f0d5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971913276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.971913276 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.1758706892
Short name T241
Test name
Test status
Simulation time 2359316037 ps
CPU time 55.94 seconds
Started Aug 15 05:55:48 PM PDT 24
Finished Aug 15 05:56:45 PM PDT 24
Peak memory 256916 kb
Host smart-edbf4dbc-dec3-40c0-8b02-1b019d8605aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758706892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1758706892 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.2410917265
Short name T25
Test name
Test status
Simulation time 6359259630 ps
CPU time 184.57 seconds
Started Aug 15 05:55:49 PM PDT 24
Finished Aug 15 05:58:54 PM PDT 24
Peak memory 370256 kb
Host smart-8bc3e186-ccbe-4ee7-9e14-d9f81a058990
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410917265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.2410917265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.639274108
Short name T679
Test name
Test status
Simulation time 7988000635 ps
CPU time 310.88 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 06:01:11 PM PDT 24
Peak memory 240200 kb
Host smart-e12c3f0f-3be5-48e3-861e-7abc2d778c2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639274108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.639274108 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2084866202
Short name T312
Test name
Test status
Simulation time 1175297029 ps
CPU time 17.61 seconds
Started Aug 15 05:55:40 PM PDT 24
Finished Aug 15 05:55:58 PM PDT 24
Peak memory 223496 kb
Host smart-afc8da81-3c39-4e0b-b6dc-1a0977dfe70b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2084866202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2084866202 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.4020624937
Short name T279
Test name
Test status
Simulation time 1576178051 ps
CPU time 29.43 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 05:56:28 PM PDT 24
Peak memory 231716 kb
Host smart-a608278b-0ab5-4de5-8017-98ae9d1524f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4020624937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.4020624937 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.713343094
Short name T106
Test name
Test status
Simulation time 14204667175 ps
CPU time 331.82 seconds
Started Aug 15 05:55:48 PM PDT 24
Finished Aug 15 06:01:20 PM PDT 24
Peak memory 491444 kb
Host smart-ebd6b430-265a-4ade-a93e-c9bc93a04235
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713343094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.713
343094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.1855773116
Short name T244
Test name
Test status
Simulation time 2572050038 ps
CPU time 76.73 seconds
Started Aug 15 05:56:00 PM PDT 24
Finished Aug 15 05:57:17 PM PDT 24
Peak memory 297588 kb
Host smart-74a8601b-618c-4475-862c-314068880a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855773116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1855773116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.3370213184
Short name T62
Test name
Test status
Simulation time 15144640548 ps
CPU time 8.47 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 05:56:09 PM PDT 24
Peak memory 217756 kb
Host smart-8be5556f-c5f4-449b-8c6e-28ab7f4df70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370213184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3370213184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2122600403
Short name T216
Test name
Test status
Simulation time 41566257 ps
CPU time 1.3 seconds
Started Aug 15 05:56:00 PM PDT 24
Finished Aug 15 05:56:02 PM PDT 24
Peak memory 216984 kb
Host smart-dadcc1e5-424b-4897-aaf7-15a7b5f9fb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122600403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2122600403 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.540838790
Short name T655
Test name
Test status
Simulation time 72974412750 ps
CPU time 4487.02 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 07:10:57 PM PDT 24
Peak memory 3542772 kb
Host smart-6dbaaa13-b116-46d4-87f9-7f78da47f0ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540838790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and
_output.540838790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.2309560013
Short name T576
Test name
Test status
Simulation time 4020686857 ps
CPU time 42.2 seconds
Started Aug 15 05:55:41 PM PDT 24
Finished Aug 15 05:56:23 PM PDT 24
Peak memory 252900 kb
Host smart-1b87d795-c625-48ff-a3e0-3f85a3ca8328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309560013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2309560013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.984662616
Short name T217
Test name
Test status
Simulation time 3753730633 ps
CPU time 284.67 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 349040 kb
Host smart-cec2af6e-b809-42ea-bf0e-51d2ddf02c87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984662616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.984662616 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.3463647268
Short name T640
Test name
Test status
Simulation time 322171288 ps
CPU time 3.54 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:12 PM PDT 24
Peak memory 217808 kb
Host smart-dbb4639b-8bec-464c-9b40-5dbdab6f8743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463647268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3463647268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_alert_test.544999292
Short name T313
Test name
Test status
Simulation time 14929062 ps
CPU time 0.77 seconds
Started Aug 15 05:55:59 PM PDT 24
Finished Aug 15 05:56:00 PM PDT 24
Peak memory 204916 kb
Host smart-fb52f5c7-a931-4049-b2ff-31699cd0ac96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544999292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.544999292 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.4233130051
Short name T721
Test name
Test status
Simulation time 13339980658 ps
CPU time 176.64 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:59:03 PM PDT 24
Peak memory 292860 kb
Host smart-344fd376-3357-4238-b95a-dd2aa5d92af8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233130051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.4233130051 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1762306476
Short name T692
Test name
Test status
Simulation time 28130766560 ps
CPU time 199.43 seconds
Started Aug 15 05:55:51 PM PDT 24
Finished Aug 15 05:59:10 PM PDT 24
Peak memory 293772 kb
Host smart-93c3de44-f748-4488-9509-8c6537b78082
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762306476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.1762306476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.653788243
Short name T301
Test name
Test status
Simulation time 8828043960 ps
CPU time 269.46 seconds
Started Aug 15 05:55:58 PM PDT 24
Finished Aug 15 06:00:28 PM PDT 24
Peak memory 230948 kb
Host smart-4ce46660-55f0-417d-b72f-db114ebf4fb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653788243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.653788243 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.4061797599
Short name T291
Test name
Test status
Simulation time 679160274 ps
CPU time 15.73 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:24 PM PDT 24
Peak memory 223580 kb
Host smart-4029b2ff-674a-4bd4-8e5c-124e01dfb900
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4061797599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.4061797599 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.3682841539
Short name T501
Test name
Test status
Simulation time 1612838764 ps
CPU time 20.82 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 05:56:31 PM PDT 24
Peak memory 223492 kb
Host smart-25390f18-db70-494f-b80a-84ae0b06b6bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3682841539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3682841539 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.2661515451
Short name T407
Test name
Test status
Simulation time 22269827034 ps
CPU time 62.08 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 05:57:10 PM PDT 24
Peak memory 218344 kb
Host smart-fd2581f6-7c63-4852-8fa9-ef3be013fec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661515451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2661515451 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.1229164086
Short name T607
Test name
Test status
Simulation time 4040680872 ps
CPU time 124.23 seconds
Started Aug 15 05:56:05 PM PDT 24
Finished Aug 15 05:58:09 PM PDT 24
Peak memory 271908 kb
Host smart-250bee6c-8e0e-45bc-9dce-7c018823a571
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229164086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.12
29164086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.4080675686
Short name T248
Test name
Test status
Simulation time 14233486781 ps
CPU time 164.43 seconds
Started Aug 15 05:55:55 PM PDT 24
Finished Aug 15 05:58:40 PM PDT 24
Peak memory 387548 kb
Host smart-b398afda-0ff6-4f75-91dd-445f698d51ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080675686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.4080675686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.76202780
Short name T415
Test name
Test status
Simulation time 982200335 ps
CPU time 5.95 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:56:14 PM PDT 24
Peak memory 217460 kb
Host smart-80ff21c9-ef88-45d3-9431-2893f0645e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76202780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.76202780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.3905743253
Short name T496
Test name
Test status
Simulation time 34970735 ps
CPU time 1.32 seconds
Started Aug 15 05:55:49 PM PDT 24
Finished Aug 15 05:55:51 PM PDT 24
Peak memory 217008 kb
Host smart-52decdaf-6885-4aa3-b8dc-6851c2d01d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905743253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3905743253 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.997560425
Short name T433
Test name
Test status
Simulation time 242264090194 ps
CPU time 4169 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 07:05:41 PM PDT 24
Peak memory 3362284 kb
Host smart-a8381f4e-ba05-48b5-85c0-72eda0ca7e96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997560425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and
_output.997560425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.3725088177
Short name T495
Test name
Test status
Simulation time 2629841064 ps
CPU time 140.35 seconds
Started Aug 15 05:56:08 PM PDT 24
Finished Aug 15 05:58:28 PM PDT 24
Peak memory 284404 kb
Host smart-389d79e5-38bc-4355-965f-b6de23b42803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725088177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3725088177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.3980581720
Short name T319
Test name
Test status
Simulation time 5434628579 ps
CPU time 162.23 seconds
Started Aug 15 05:56:00 PM PDT 24
Finished Aug 15 05:58:43 PM PDT 24
Peak memory 361396 kb
Host smart-4b1e94c7-0f5e-462a-a3d2-4b18226b607f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980581720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3980581720 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.19383733
Short name T3
Test name
Test status
Simulation time 3075334096 ps
CPU time 53.5 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 05:57:04 PM PDT 24
Peak memory 223664 kb
Host smart-5ad13daa-93ed-429d-b3fc-7359470bd6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19383733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.19383733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1028900089
Short name T674
Test name
Test status
Simulation time 64763594418 ps
CPU time 1337.9 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 06:18:29 PM PDT 24
Peak memory 691088 kb
Host smart-43901657-cf16-44c4-a07b-9c436093d322
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1028900089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1028900089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3374635075
Short name T402
Test name
Test status
Simulation time 15463411 ps
CPU time 0.81 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 05:56:12 PM PDT 24
Peak memory 204948 kb
Host smart-5534d0e0-778d-4e61-b2a6-66f6700b4445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374635075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3374635075 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.1385786014
Short name T341
Test name
Test status
Simulation time 12215701188 ps
CPU time 253.88 seconds
Started Aug 15 05:55:51 PM PDT 24
Finished Aug 15 06:00:05 PM PDT 24
Peak memory 442668 kb
Host smart-abf36bb3-c9b7-480a-babb-4a40a4b6aa7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385786014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1385786014 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.2941797282
Short name T332
Test name
Test status
Simulation time 106800892367 ps
CPU time 140.63 seconds
Started Aug 15 05:55:51 PM PDT 24
Finished Aug 15 05:58:12 PM PDT 24
Peak memory 325620 kb
Host smart-ae85bd36-39fd-4145-8aef-391dd787d454
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941797282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.2941797282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.179744250
Short name T463
Test name
Test status
Simulation time 9092338206 ps
CPU time 281.52 seconds
Started Aug 15 05:56:16 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 232368 kb
Host smart-bbaad958-de78-4fde-8c91-51c0d8368d23
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179744250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.179744250 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2419864015
Short name T671
Test name
Test status
Simulation time 4302277210 ps
CPU time 25.76 seconds
Started Aug 15 05:56:11 PM PDT 24
Finished Aug 15 05:56:37 PM PDT 24
Peak memory 224540 kb
Host smart-7d5540ee-4eba-40b4-b5ab-02fffcd22a37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2419864015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2419864015 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.379825547
Short name T470
Test name
Test status
Simulation time 643825932 ps
CPU time 23.48 seconds
Started Aug 15 05:55:55 PM PDT 24
Finished Aug 15 05:56:18 PM PDT 24
Peak memory 231552 kb
Host smart-b5ed8187-292d-412b-9ab8-230d08b56cfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=379825547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.379825547 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.1304932561
Short name T693
Test name
Test status
Simulation time 1162720977 ps
CPU time 7.06 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 05:56:15 PM PDT 24
Peak memory 218248 kb
Host smart-49458caa-9e81-4a7f-b09d-0ffc9d61ddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304932561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1304932561 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.1092697908
Short name T593
Test name
Test status
Simulation time 9106309042 ps
CPU time 148.27 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 05:58:37 PM PDT 24
Peak memory 340624 kb
Host smart-fc0daf91-e45f-44c3-943f-d5a2348c3dbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092697908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.10
92697908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.1170852579
Short name T221
Test name
Test status
Simulation time 1236907473 ps
CPU time 92.72 seconds
Started Aug 15 05:55:52 PM PDT 24
Finished Aug 15 05:57:25 PM PDT 24
Peak memory 268360 kb
Host smart-bcd0ae23-1ba1-431b-9805-bfaf3f8bc6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170852579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1170852579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.2352768311
Short name T554
Test name
Test status
Simulation time 3392320104 ps
CPU time 5.15 seconds
Started Aug 15 05:55:51 PM PDT 24
Finished Aug 15 05:55:56 PM PDT 24
Peak memory 217704 kb
Host smart-73ab29d0-cbc3-4b41-8652-c8546eb61f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352768311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2352768311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1340034267
Short name T594
Test name
Test status
Simulation time 37378839 ps
CPU time 1.47 seconds
Started Aug 15 05:55:54 PM PDT 24
Finished Aug 15 05:55:55 PM PDT 24
Peak memory 217640 kb
Host smart-300b13e3-664d-458d-917b-87df85a61b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340034267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1340034267 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1310405330
Short name T347
Test name
Test status
Simulation time 17445344135 ps
CPU time 1931.52 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 06:28:21 PM PDT 24
Peak memory 1230692 kb
Host smart-d8e23497-637c-459e-a939-876fd5f2f76b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310405330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1310405330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.3014221736
Short name T506
Test name
Test status
Simulation time 57444338667 ps
CPU time 99.2 seconds
Started Aug 15 05:55:58 PM PDT 24
Finished Aug 15 05:57:37 PM PDT 24
Peak memory 291416 kb
Host smart-a9dab5cc-178a-443d-a685-53967f30a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014221736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3014221736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.2155519298
Short name T238
Test name
Test status
Simulation time 13423669673 ps
CPU time 307.23 seconds
Started Aug 15 05:56:12 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 515624 kb
Host smart-95be195c-6b11-4808-b22e-c9fcf2d02961
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155519298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2155519298 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.264144414
Short name T237
Test name
Test status
Simulation time 2282350998 ps
CPU time 26.58 seconds
Started Aug 15 05:55:54 PM PDT 24
Finished Aug 15 05:56:21 PM PDT 24
Peak memory 218080 kb
Host smart-19189f9e-1ee8-4eb7-aa93-bf3ea0c74713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264144414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.264144414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.1770578167
Short name T258
Test name
Test status
Simulation time 3922072251 ps
CPU time 371.28 seconds
Started Aug 15 05:56:00 PM PDT 24
Finished Aug 15 06:02:11 PM PDT 24
Peak memory 467248 kb
Host smart-a9072905-3351-44de-aefa-06a4c44f4768
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1770578167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1770578167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_alert_test.637327710
Short name T690
Test name
Test status
Simulation time 23041874 ps
CPU time 0.87 seconds
Started Aug 15 05:56:06 PM PDT 24
Finished Aug 15 05:56:08 PM PDT 24
Peak memory 204956 kb
Host smart-b5fe7788-9f50-45fe-ac10-e79b080666fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637327710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.637327710 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.2620078221
Short name T699
Test name
Test status
Simulation time 4597068042 ps
CPU time 133.99 seconds
Started Aug 15 05:55:55 PM PDT 24
Finished Aug 15 05:58:09 PM PDT 24
Peak memory 273888 kb
Host smart-9cbaed8a-c37b-44d5-aab8-2d7006b0349e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620078221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2620078221 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3857445594
Short name T315
Test name
Test status
Simulation time 50077104787 ps
CPU time 62.4 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 05:57:03 PM PDT 24
Peak memory 253420 kb
Host smart-42bd9806-c1b8-4078-bf85-9bef24b7628d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857445594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.3857445594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.905196957
Short name T155
Test name
Test status
Simulation time 7431327305 ps
CPU time 678.42 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 238044 kb
Host smart-f8cc2e14-64a4-4574-8895-6549b3257723
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905196957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.905196957 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.453994143
Short name T516
Test name
Test status
Simulation time 530092181 ps
CPU time 9.03 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 05:56:19 PM PDT 24
Peak memory 219468 kb
Host smart-0e2ea8fd-4990-42ea-9f44-d8fdfb2180a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453994143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.453994143 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.94258912
Short name T354
Test name
Test status
Simulation time 361277613 ps
CPU time 7.21 seconds
Started Aug 15 05:55:52 PM PDT 24
Finished Aug 15 05:55:59 PM PDT 24
Peak memory 217184 kb
Host smart-b8f2b435-560b-4a4b-aff1-456617793d92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=94258912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.94258912 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.3877337864
Short name T462
Test name
Test status
Simulation time 5750951256 ps
CPU time 23.49 seconds
Started Aug 15 05:55:52 PM PDT 24
Finished Aug 15 05:56:15 PM PDT 24
Peak memory 218544 kb
Host smart-49693506-13a6-43b5-97d3-bd9b0aa7057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877337864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3877337864 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.2707982451
Short name T404
Test name
Test status
Simulation time 4509935825 ps
CPU time 320.16 seconds
Started Aug 15 05:55:53 PM PDT 24
Finished Aug 15 06:01:13 PM PDT 24
Peak memory 348948 kb
Host smart-91b32020-a72a-4914-8fb5-eb66fcd89f5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707982451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.27
07982451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.898524949
Short name T460
Test name
Test status
Simulation time 16728538094 ps
CPU time 70.71 seconds
Started Aug 15 05:56:09 PM PDT 24
Finished Aug 15 05:57:20 PM PDT 24
Peak memory 286552 kb
Host smart-b79700bf-f193-498b-a0be-a5cd098b52ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898524949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.898524949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2402883451
Short name T250
Test name
Test status
Simulation time 509549207 ps
CPU time 3.16 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 05:56:13 PM PDT 24
Peak memory 217784 kb
Host smart-229b0126-78d3-4b13-8816-922db69ae9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402883451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2402883451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.2477280163
Short name T56
Test name
Test status
Simulation time 43023723 ps
CPU time 1.44 seconds
Started Aug 15 05:55:58 PM PDT 24
Finished Aug 15 05:56:00 PM PDT 24
Peak memory 217552 kb
Host smart-fcb0fd72-f82d-4977-b3a4-a88d9aeb607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477280163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2477280163 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.2041785317
Short name T322
Test name
Test status
Simulation time 258557340301 ps
CPU time 2362.46 seconds
Started Aug 15 05:56:01 PM PDT 24
Finished Aug 15 06:35:24 PM PDT 24
Peak memory 2486960 kb
Host smart-1d76a12f-9dfd-4d83-b3d2-2dfa65aafb07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041785317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.2041785317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.1023811180
Short name T264
Test name
Test status
Simulation time 4354470280 ps
CPU time 253.18 seconds
Started Aug 15 05:56:15 PM PDT 24
Finished Aug 15 06:00:29 PM PDT 24
Peak memory 326696 kb
Host smart-8eeb88d2-e5d0-4206-a0ae-864d1f5b7144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023811180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1023811180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.4157064009
Short name T488
Test name
Test status
Simulation time 6002725453 ps
CPU time 144.99 seconds
Started Aug 15 05:56:10 PM PDT 24
Finished Aug 15 05:58:35 PM PDT 24
Peak memory 283192 kb
Host smart-153f2880-deee-47fc-828b-d2ff817e05a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157064009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.4157064009 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1539182530
Short name T83
Test name
Test status
Simulation time 9724841638 ps
CPU time 39.77 seconds
Started Aug 15 05:56:07 PM PDT 24
Finished Aug 15 05:56:47 PM PDT 24
Peak memory 223824 kb
Host smart-c0707c2d-2b33-4ed4-8775-7e1d4d2ae7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539182530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1539182530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.1656662148
Short name T51
Test name
Test status
Simulation time 2307961809 ps
CPU time 66.22 seconds
Started Aug 15 05:55:51 PM PDT 24
Finished Aug 15 05:56:58 PM PDT 24
Peak memory 256980 kb
Host smart-5eeb7623-dc09-4681-9d91-20b54ab77396
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1656662148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1656662148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%