Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15811557	1			T1	191572		T2	3099		T3	279
all_values[1]	15811557	1			T1	191572		T2	3099		T3	279
all_values[2]	15811557	1			T1	191572		T2	3099		T3	279

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

465958

1

T1

2354

T2

4

T3

3

auto[1]

46968713

1

T1

572362

T2

9293

T3

834

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47226231

1

T1

574146

T2

9204

T3

765

auto[1]

208440

1

T1

570

T2

93

T3

72

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	164002	1			T3	1		T12	1		T13	277
all_values[0]	auto[0]	auto[1]	1297	1			T3	2		T13	4		T40	2
all_values[0]	auto[1]	auto[0]	15578075	1			T1	191382		T2	3068		T3	254
all_values[0]	auto[1]	auto[1]	68183	1			T1	190		T2	31		T3	22
all_values[1]	auto[0]	auto[0]	136025	1			T1	2353		T2	2		T12	2
all_values[1]	auto[0]	auto[1]	878	1			T1	1		T14	1		T17	4
all_values[1]	auto[1]	auto[0]	15606052	1			T1	189029		T2	3066		T3	255
all_values[1]	auto[1]	auto[1]	68602	1			T1	189		T2	31		T3	24
all_values[2]	auto[0]	auto[0]	162762	1			T2	2		T40	610		T35	433
all_values[2]	auto[0]	auto[1]	994	1			T40	2		T35	4		T36	2
all_values[2]	auto[1]	auto[0]	15579315	1			T1	191382		T2	3066		T3	255
all_values[2]	auto[1]	auto[1]	68486	1			T1	190		T2	31		T3	24