Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55402 |
1 |
|
|
T1 |
250 |
|
T2 |
72 |
|
T3 |
2 |
auto[1] |
51480 |
1 |
|
|
T3 |
30 |
|
T13 |
164 |
|
T14 |
136 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
26657 |
1 |
|
|
T1 |
54 |
|
T2 |
26 |
|
T3 |
10 |
lower_val |
26217 |
1 |
|
|
T1 |
62 |
|
T2 |
13 |
|
T3 |
9 |
zero_val |
910 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
53298 |
1 |
|
|
T1 |
106 |
|
T2 |
40 |
|
T3 |
18 |
lower_val |
53584 |
1 |
|
|
T1 |
144 |
|
T2 |
32 |
|
T3 |
14 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6802 |
1 |
|
|
T1 |
23 |
|
T2 |
14 |
|
T12 |
35 |
higher_val |
higher_val |
auto[1] |
6431 |
1 |
|
|
T3 |
6 |
|
T13 |
20 |
|
T14 |
12 |
higher_val |
lower_val |
auto[0] |
6907 |
1 |
|
|
T1 |
31 |
|
T2 |
12 |
|
T12 |
48 |
higher_val |
lower_val |
auto[1] |
6517 |
1 |
|
|
T3 |
4 |
|
T13 |
16 |
|
T14 |
12 |
lower_val |
higher_val |
auto[0] |
6804 |
1 |
|
|
T1 |
27 |
|
T2 |
8 |
|
T12 |
42 |
lower_val |
higher_val |
auto[1] |
6369 |
1 |
|
|
T3 |
4 |
|
T13 |
14 |
|
T14 |
24 |
lower_val |
lower_val |
auto[0] |
6745 |
1 |
|
|
T1 |
35 |
|
T2 |
5 |
|
T12 |
40 |
lower_val |
lower_val |
auto[1] |
6299 |
1 |
|
|
T3 |
5 |
|
T13 |
16 |
|
T14 |
16 |
zero_val |
higher_val |
auto[0] |
345 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
88 |
1 |
|
|
T38 |
1 |
|
T23 |
4 |
|
T64 |
1 |
zero_val |
lower_val |
auto[0] |
383 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
94 |
1 |
|
|
T14 |
2 |
|
T75 |
1 |
|
T38 |
1 |