Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15811557	1			T1	191572		T2	3099		T3	279
all_pins[1]	15811557	1			T1	191572		T2	3099		T3	279
all_pins[2]	15811557	1			T1	191572		T2	3099		T3	279

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47024709	1			T1	574526		T2	9266		T3	813
values[0x1]	409962	1			T1	190		T2	31		T3	24
transitions[0x0=>0x1]	407878	1			T1	190		T2	31		T3	24
transitions[0x1=>0x0]	407897	1			T1	190		T2	31		T3	24

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15743374	1			T1	191382		T2	3068		T3	257
all_pins[0]	values[0x1]	68183	1			T1	190		T2	31		T3	22
all_pins[0]	transitions[0x0=>0x1]	68166	1			T1	190		T2	31		T3	22
all_pins[0]	transitions[0x1=>0x0]	62	1			T3	2		T39	10		T66	2
all_pins[1]	values[0x0]	15811478	1			T1	191572		T2	3099		T3	277
all_pins[1]	values[0x1]	79	1			T3	2		T39	10		T66	2
all_pins[1]	transitions[0x0=>0x1]	68	1			T3	2		T39	10		T66	2
all_pins[1]	transitions[0x1=>0x0]	341689	1			T22	17576		T23	7227		T24	18772
all_pins[2]	values[0x0]	15469857	1			T1	191572		T2	3099		T3	279
all_pins[2]	values[0x1]	341700	1			T22	17576		T23	7227		T24	18772
all_pins[2]	transitions[0x0=>0x1]	339644	1			T22	17470		T23	7183		T24	18651
all_pins[2]	transitions[0x1=>0x0]	66146	1			T1	190		T2	31		T3	22