Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56299 |
1 |
|
|
T1 |
124 |
|
T2 |
43 |
|
T3 |
16 |
auto[1] |
3538 |
1 |
|
|
T2 |
8 |
|
T12 |
104 |
|
T13 |
11 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
25431 |
1 |
|
|
T1 |
35 |
|
T2 |
24 |
|
T3 |
3 |
auto[1] |
34406 |
1 |
|
|
T1 |
89 |
|
T2 |
27 |
|
T3 |
13 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46188 |
1 |
|
|
T1 |
124 |
|
T2 |
38 |
|
T3 |
16 |
auto[1] |
13649 |
1 |
|
|
T2 |
13 |
|
T12 |
136 |
|
T13 |
22 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13649 |
1 |
|
|
T2 |
13 |
|
T12 |
136 |
|
T13 |
22 |
sw_kmac_invalid_sideload |
46188 |
1 |
|
|
T1 |
124 |
|
T2 |
38 |
|
T3 |
16 |
app_valid_sideload |
13649 |
1 |
|
|
T2 |
13 |
|
T12 |
136 |
|
T13 |
22 |
app_invalid_sideload |
46188 |
1 |
|
|
T1 |
124 |
|
T2 |
38 |
|
T3 |
16 |