Group : kmac_env_pkg::kmac_env_cov::sideload_cg
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Group : kmac_env_pkg::kmac_env_cov::sideload_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::sideload_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::sideload_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
in_app_keymgr 2 0 2 100.00 100 1 1 2
kmac_mode 2 0 2 100.00 100 1 1 2
sideload 2 0 2 100.00 100 1 1 2


Crosses for Group kmac_env_pkg::kmac_env_cov::sideload_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sideload_cross 4 0 4 100.00 100 1 1 0


Summary for Variable in_app_keymgr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for in_app_keymgr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56299 1 T1 124 T2 43 T3 16
auto[1] 3538 1 T2 8 T12 104 T13 11



Summary for Variable kmac_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25431 1 T1 35 T2 24 T3 3
auto[1] 34406 1 T1 89 T2 27 T3 13



Summary for Variable sideload

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sideload

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 46188 1 T1 124 T2 38 T3 16
auto[1] 13649 1 T2 13 T12 136 T13 22



Summary for Cross sideload_cross

Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 4 0 4 100.00


User Defined Cross Bins for sideload_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_kmac_valid_sideload 13649 1 T2 13 T12 136 T13 22
sw_kmac_invalid_sideload 46188 1 T1 124 T2 38 T3 16
app_valid_sideload 13649 1 T2 13 T12 136 T13 22
app_invalid_sideload 46188 1 T1 124 T2 38 T3 16

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%