Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6129579 |
1 |
|
|
T1 |
19560 |
|
T2 |
3635 |
|
T3 |
2830 |
auto[1] |
9366086 |
1 |
|
|
T1 |
27998 |
|
T2 |
5780 |
|
T3 |
4062 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15464888 |
1 |
|
|
T1 |
47457 |
|
T2 |
9400 |
|
T3 |
6878 |
triple_byte_access |
10261 |
1 |
|
|
T1 |
38 |
|
T2 |
8 |
|
T3 |
5 |
halfword_access |
10224 |
1 |
|
|
T1 |
29 |
|
T2 |
3 |
|
T3 |
7 |
byte_access |
10292 |
1 |
|
|
T1 |
34 |
|
T2 |
4 |
|
T3 |
2 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6098802 |
1 |
|
|
T1 |
19459 |
|
T2 |
3620 |
|
T3 |
2816 |
auto[0] |
triple_byte_access |
10261 |
1 |
|
|
T1 |
38 |
|
T2 |
8 |
|
T3 |
5 |
auto[0] |
halfword_access |
10224 |
1 |
|
|
T1 |
29 |
|
T2 |
3 |
|
T3 |
7 |
auto[0] |
byte_access |
10292 |
1 |
|
|
T1 |
34 |
|
T2 |
4 |
|
T3 |
2 |
auto[1] |
word_access |
9366086 |
1 |
|
|
T1 |
27998 |
|
T2 |
5780 |
|
T3 |
4062 |