Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15803784	1			T1	17072		T3	1035		T4	24202
all_values[1]	15803784	1			T1	17072		T3	1035		T4	24202
all_values[2]	15803784	1			T1	17072		T3	1035		T4	24202

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

543591

1

T4

785

T14

244

T16

373

auto[1]

46867761

1

T1

51216

T3

3105

T4

71821

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47198538

1

T1

50736

T3

2673

T4

71844

auto[1]

212814

1

T1

480

T3

432

T4

762

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	182146	1			T20	1798		T37	505		T6	4
all_values[0]	auto[0]	auto[1]	1227	1			T20	2		T37	6		T38	2
all_values[0]	auto[1]	auto[0]	15550700	1			T1	16912		T3	891		T4	23948
all_values[0]	auto[1]	auto[1]	69711	1			T1	160		T3	144		T4	254
all_values[1]	auto[0]	auto[0]	199478	1			T4	503		T14	243		T16	299
all_values[1]	auto[0]	auto[1]	962	1			T4	3		T14	1		T16	4
all_values[1]	auto[1]	auto[0]	15533368	1			T1	16912		T3	891		T4	23445
all_values[1]	auto[1]	auto[1]	69976	1			T1	160		T3	144		T4	251
all_values[2]	auto[0]	auto[0]	158833	1			T4	278		T16	69		T18	9
all_values[2]	auto[0]	auto[1]	945	1			T4	1		T16	1		T18	1
all_values[2]	auto[1]	auto[0]	15574013	1			T1	16912		T3	891		T4	23670
all_values[2]	auto[1]	auto[1]	69993	1			T1	160		T3	144		T4	253