Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53514 |
1 |
|
|
T1 |
2 |
|
T3 |
196 |
|
T4 |
342 |
auto[1] |
54384 |
1 |
|
|
T1 |
214 |
|
T14 |
2 |
|
T18 |
22 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
26908 |
1 |
|
|
T1 |
42 |
|
T3 |
50 |
|
T4 |
84 |
lower_val |
26547 |
1 |
|
|
T1 |
60 |
|
T3 |
58 |
|
T4 |
94 |
zero_val |
870 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
54338 |
1 |
|
|
T1 |
82 |
|
T3 |
100 |
|
T4 |
194 |
lower_val |
53558 |
1 |
|
|
T1 |
134 |
|
T3 |
96 |
|
T4 |
148 |
zero_val |
2 |
1 |
|
|
T159 |
2 |
|
- |
- |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6622 |
1 |
|
|
T3 |
20 |
|
T4 |
47 |
|
T16 |
16 |
higher_val |
higher_val |
auto[1] |
6926 |
1 |
|
|
T1 |
14 |
|
T18 |
4 |
|
T20 |
25 |
higher_val |
lower_val |
auto[0] |
6591 |
1 |
|
|
T3 |
30 |
|
T4 |
37 |
|
T16 |
12 |
higher_val |
lower_val |
auto[1] |
6768 |
1 |
|
|
T1 |
28 |
|
T18 |
4 |
|
T20 |
21 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T159 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
6704 |
1 |
|
|
T3 |
31 |
|
T4 |
53 |
|
T16 |
10 |
lower_val |
higher_val |
auto[1] |
6682 |
1 |
|
|
T1 |
17 |
|
T18 |
3 |
|
T20 |
25 |
lower_val |
lower_val |
auto[0] |
6617 |
1 |
|
|
T1 |
1 |
|
T3 |
27 |
|
T4 |
41 |
lower_val |
lower_val |
auto[1] |
6544 |
1 |
|
|
T1 |
42 |
|
T18 |
5 |
|
T20 |
29 |
zero_val |
higher_val |
auto[0] |
337 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T17 |
3 |
zero_val |
higher_val |
auto[1] |
94 |
1 |
|
|
T24 |
1 |
|
T160 |
2 |
|
T40 |
7 |
zero_val |
lower_val |
auto[0] |
350 |
1 |
|
|
T1 |
1 |
|
T14 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
89 |
1 |
|
|
T82 |
2 |
|
T40 |
3 |
|
T25 |
2 |