Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 322 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 2790 1 T17 28 T18 4 T20 30
len_5001_7500 6565 1 T17 68 T18 6 T20 69
len_2501_5000 1569 1 T17 10 T20 13 T24 4
len_1025_2500 979 1 T17 9 T18 2 T20 15
len_769_1024 5219 1 T1 25 T4 34 T14 1
len_513_768 5797 1 T1 36 T4 44 T14 1
len_257_512 5983 1 T1 19 T4 49 T16 5
len_0_256 17867 1 T1 28 T3 98 T4 44
len_keccak_block_sizes[72] 29 1 T84 1 T180 1 T181 1
len_keccak_block_sizes[104] 32 1 T30 1 T31 1 T26 1
len_keccak_block_sizes[136] 37 1 T160 1 T40 1 T25 1
len_keccak_block_sizes[144] 30 1 T23 1 T29 1 T32 1
len_keccak_block_sizes[168] 22 1 T1 1 T37 1 T39 1
len_1 75 1 T3 1 T27 1 T81 1
len_0 456 1 T1 1 T3 1 T17 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%