Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15803784	1			T1	17072		T3	1035		T4	24202
all_pins[1]	15803784	1			T1	17072		T3	1035		T4	24202
all_pins[2]	15803784	1			T1	17072		T3	1035		T4	24202

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47048185	1			T1	51056		T3	2961		T4	72352
values[0x1]	363167	1			T1	160		T3	144		T4	254
transitions[0x0=>0x1]	361414	1			T1	160		T3	144		T4	254
transitions[0x1=>0x0]	361429	1			T1	160		T3	144		T4	254

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15734073	1			T1	16912		T3	891		T4	23948
all_pins[0]	values[0x1]	69711	1			T1	160		T3	144		T4	254
all_pins[0]	transitions[0x0=>0x1]	69702	1			T1	160		T3	144		T4	254
all_pins[0]	transitions[0x1=>0x0]	79	1			T25	5		T42	5		T173	4
all_pins[1]	values[0x0]	15803696	1			T1	17072		T3	1035		T4	24202
all_pins[1]	values[0x1]	88	1			T25	5		T42	5		T173	4
all_pins[1]	transitions[0x0=>0x1]	78	1			T25	5		T42	5		T173	4
all_pins[1]	transitions[0x1=>0x0]	293358	1			T23	1525		T24	3287		T30	315
all_pins[2]	values[0x0]	15510416	1			T1	17072		T3	1035		T4	24202
all_pins[2]	values[0x1]	293368	1			T23	1525		T24	3287		T30	315
all_pins[2]	transitions[0x0=>0x1]	291634	1			T23	1525		T24	3267		T30	315
all_pins[2]	transitions[0x1=>0x0]	67992	1			T1	160		T3	144		T4	254