Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	707	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5263	1			T1	13		T4	33		T14	1
len_601_800	12118	1			T1	34		T4	62		T16	12
len_401_600	8018	1			T1	31		T4	32		T16	3
len_201_400	4065	1			T1	9		T4	16		T14	1
len_65_200	6536	1			T1	11		T3	46		T4	16
len_min_for_xof_require_squeeze	68	1			T1	1		T3	1		T18	1
len_keccak_block_sizes[72]	55	1			T3	1		T82	9		T182	1
len_keccak_block_sizes[104]	63	1			T3	1		T81	1		T82	9
len_keccak_block_sizes[136]	60	1			T24	1		T81	2		T82	9
len_keccak_block_sizes[144]	39	1			T3	1		T20	1		T38	1
len_keccak_block_sizes[168]	29	1			T183	1		T25	2		T168	1
len_datapath_width	1019	1			T3	4		T4	2		T17	2
len_2_63	14907	1			T1	5		T3	48		T4	6
len_1	59	1			T81	2		T182	1		T160	1